Searched refs:L1 (Results 1 - 25 of 42) sorted by last modified time

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/linux-master/drivers/pci/pcie/
H A Daspm.c3 * Enable PCIe link L0s/L1 state and Clock Power Management
87 * Save L1 substate configuration. The ASPM L0s/L1 configuration
111 * In case BIOS enabled L1.2 when resuming, we need to disable it first
133 /* Make sure L0s/L1 are disabled before updating L1SS config */
145 * Disable L1.2 on this downstream endpoint device first, followed
155 * in PCI_L1SS_CTL1 must be programmed *before* setting the L1.2
177 /* Restore L0s/L1 if they were enabled */
195 #define ASPM_STATE_L1 (4) /* L1 state */
196 #define ASPM_STATE_L1_1 (8) /* ASPM L1
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/linux-master/arch/x86/events/intel/
H A Dds.c82 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */
179 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
196 * bit 0: hit L1 data cache
226 * L1 info only valid for following events:
252 *val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
/linux-master/arch/powerpc/perf/
H A Dpower10-pmu.c29 * | | | *- L1/L2/L3 cache_sel | |*-radix_scope_qual
133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
135 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_LD_PREFETCH_CACHE_LINE_MISS);
136 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
137 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
138 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
139 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ);
/linux-master/tools/perf/util/
H A Dmem-events.c278 "L1",
325 "L1",
626 if (lvl & P(LVL, L1 )) stats->ld_l1hit++;
689 if (lvl & P(LVL, L1 )) stats->st_l1hit++;
692 if (lvl & P(LVL, L1)) stats->st_l1miss++;
H A Dparse-events.l171 lc_type (L1-dcache|l1-d|l1d|L1-data|L1-icache|l1-i|l1i|L1-instruction|LLC|L2|dTLB|d-tlb|Data-TLB|iTLB|i-tlb|Instruction-TLB|branch|branches|bpu|btb|bpc|node)
/linux-master/arch/riscv/lib/
H A Dtishift.S10 beqz a2, .L1
21 .L1:
/linux-master/drivers/perf/
H A Ddwc_pcie_pmu.c197 DWC_PCIE_PMU_TIME_BASE_EVENT_ATTR(L1, 0x04),
/linux-master/arch/x86/events/amd/
H A Dibs.c781 /* L1 Hit */
783 return L(L1) | LN(L1);
/linux-master/security/apparmor/include/
H A Dperms.h168 * TODO: optimize the walk, currently does subwalk of L2 for each P in L1
186 #define xcheck_ns_labels(L1, L2, FN, args...) \
189 fn_for_each((L1), __p1, FN(__p1, (L2), args)); \
193 #define xcheck_labels_profiles(L1, L2, FN, args...) \
194 xcheck_ns_labels((L1), (L2), xcheck_ns_profile_label, (FN), args)
196 #define xcheck_labels(L1, L2, P, FN1, FN2) \
197 xcheck(fn_for_each((L1), (P), (FN1)), fn_for_each((L2), (P), (FN2)))
H A Dlabel.h163 #define next_comb(I, L1, L2) \
173 /* for each combination of P1 in L1, and P2 in L2 */
174 #define label_for_each_comb(I, L1, L2, P1, P2) \
176 ((P1) = (L1)->vec[(I).i]) && ((P2) = (L2)->vec[(I).j]); \
177 (I) = next_comb(I, L1, L2))
179 #define fn_for_each_comb(L1, L2, P1, P2, FN) \
183 label_for_each_comb(i, (L1), (L2), (P1), (P2)) { \
243 #define fn_for_each2_XXX(L1, L2, P, FN, ...) \
247 label_for_each ## __VA_ARGS__(i, (L1), (L2), (P)) { \
253 #define fn_for_each_in_merge(L1, L
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/linux-master/drivers/pinctrl/aspeed/
H A Dpinctrl-aspeed-g5.c657 #define L1 82 macro
658 SIG_EXPR_LIST_DECL_SINGLE(L1, SCL6, I2C6, I2C6_DESC);
659 PIN_DECL_1(L1, GPIOK2, SCL6);
665 FUNC_GROUP_DECL(I2C6, L1, N2);
2047 ASPEED_PINCTRL_PIN(L1),
H A Dpinctrl-aspeed-g4.c1489 #define L1 180 macro
1490 SIG_EXPR_LIST_DECL_SINGLE(L1, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
1491 SIG_EXPR_LIST_DECL_SINGLE(L1, ADC4, ADC4);
1492 PIN_DECL_(L1, SIG_EXPR_LIST_PTR(L1, GPIOW4), SIG_EXPR_LIST_PTR(L1, ADC4));
1493 FUNC_GROUP_DECL(ADC4, L1);
2047 ASPEED_PINCTRL_PIN(L1),
2500 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L1, L1, SCUA
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/linux-master/arch/arc/kernel/
H A Dentry-compact.S152 ; if L2 IRQ interrupted a L1 ISR, disable preemption
154 ; This is to avoid a potential L1-L2-L1 scenario
155 ; -L1 IRQ taken
156 ; -L2 interrupts L1 (before L1 ISR could run)
160 ; But both L1 and L2 re-enabled, so another L1 can be taken
161 ; while prev L1 is still unserviced
165 ; L2 interrupting L1 implie
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/linux-master/arch/alpha/lib/
H A Dev6-memcpy.S18 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
85 wh64 ($7) # L1 : memory subsystem hint: 64 bytes at
H A Dev6-memset.S17 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
161 wh64 ($4) # L1 : memory subsystem write hint
339 wh64 ($4) # L1 : memory subsystem write hint
527 wh64 ($4) # L1 : memory subsystem write hint
H A Dev6-clear_user.S20 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
139 wh64 ($3) # .. .. .. L1 : memory subsystem hint
/linux-master/arch/m68k/lib/
H A Dudivsi3.S144 L1: addl d0,d0 | shift reg pair (p,a) one bit left label
152 jcc L1
H A Ddivsi3.S95 jpl L1
102 L1: movel sp@(8), d0 /* d0 = dividend */ label
/linux-master/arch/arm/mm/
H A Dproc-v7.S84 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
445 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
451 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
H A Dproc-macros.S271 mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
H A Dcache-v7.S31 * the L1; however, the L1 comes out of reset in an undefined state, so
43 mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR
190 * working outwards from L1 cache. This is done using Set/Way based cache
/linux-master/arch/arm/mach-omap2/
H A Dsleep44xx.S47 * 1 - CPUx L1 and logic lost: MPUSS CSWR
48 * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
49 * 3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF
67 * Flush all data from the L1 data cache before disabling
75 mov r1, #0xFF @ clean seucre L1
/linux-master/arch/alpha/boot/
H A Dbootpz.c108 * code has the L1 page table identity-map itself in the second PTE
109 * in the L1 page table. Thus the L1-page is virtually addressable
113 #define L1 ((unsigned long *) 0x200802000) macro
125 pcb_va->ptbr = L1[1] >> 32;
H A Dmain.c53 * code has the L1 page table identity-map itself in the second PTE
54 * in the L1 page table. Thus the L1-page is virtually addressable
59 #define L1 ((unsigned long *) 0x200802000) macro
71 pcb_va->ptbr = L1[1] >> 32;
H A Dbootp.c59 * code has the L1 page table identity-map itself in the second PTE
60 * in the L1 page table. Thus the L1-page is virtually addressable
65 #define L1 ((unsigned long *) 0x200802000) macro
77 pcb_va->ptbr = L1[1] >> 32;

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