| /linux-master/arch/m68k/ifpsp060/src/ |
| H A D | fplsp.S | 8253 lea LOGTBL(%pc),%a0 # BASE ADDRESS OF 1/F AND LOG(F)
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| /linux-master/arch/sparc/kernel/ |
| H A D | sun4v_tlb_miss.S | 10 /* Load ITLB fault information into VADDR and CTX, using BASE. */
11 #define LOAD_ITLB_INFO(BASE, VADDR, CTX) \
12 ldx [BASE + HV_FAULT_I_ADDR_OFFSET], VADDR; \
13 ldx [BASE + HV_FAULT_I_CTX_OFFSET], CTX;
15 /* Load DTLB fault information into VADDR and CTX, using BASE. */
16 #define LOAD_DTLB_INFO(BASE, VADDR, CTX) \
17 ldx [BASE + HV_FAULT_D_ADDR_OFFSET], VADDR; \
18 ldx [BASE + HV_FAULT_D_CTX_OFFSET], CTX;
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| /linux-master/drivers/gpu/drm/amd/display/dc/gpio/dce120/ |
| H A D | hw_translate_dce120.c | 48 #define BASE(seg) \ macro
52 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
55 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| H A D | hw_factory_dce120.c | 57 #define BASE(seg) \ macro
61 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn10/ |
| H A D | hw_translate_dcn10.c | 48 #define BASE(seg) \ macro
52 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
55 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| H A D | hw_factory_dcn10.c | 54 #define BASE(seg) \ macro
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
61 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/net/ethernet/smsc/ |
| H A D | smc9194.h | 99 #define BASE 2 macro
|
| /linux-master/include/linux/ |
| H A D | zutil.h | 53 #define BASE 65521L /* largest prime smaller than 65536 */ macro
55 /* NMAX is the largest n such that 255n(n+1)/2 + (n+1)(BASE-1) <= 2^32-1 */
100 s1 %= BASE;
101 s2 %= BASE;
|
| /linux-master/arch/m68k/fpsp040/ |
| H A D | slogn.S | 356 lea LOGTBL,%a0 | ...BASE ADDRESS OF 1/F AND LOG(F)
|
| /linux-master/arch/mips/include/asm/mips-boards/ |
| H A D | bonito64.h | 411 #define BONITO_PCIMEMBASECFGBASE(WIN, BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)
|
| /linux-master/arch/mips/kernel/ |
| H A D | traps.c | 504 #define BASE 0x03e00000 macro
545 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
585 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
716 #define RS BASE
|
| /linux-master/arch/sparc/net/ |
| H A D | bpf_jit_comp_32.c | 181 #define emit_loadptr(BASE, STRUCT, FIELD, DEST) \
184 *prog++ = LDPTRI | RS1(BASE) | S13(_off) | RD(DEST); \
187 #define emit_load32(BASE, STRUCT, FIELD, DEST) \
190 *prog++ = LD32I | RS1(BASE) | S13(_off) | RD(DEST); \
193 #define emit_load16(BASE, STRUCT, FIELD, DEST) \
196 *prog++ = LD16I | RS1(BASE) | S13(_off) | RD(DEST); \
199 #define __emit_load8(BASE, STRUCT, FIELD, DEST) \
201 *prog++ = LD8I | RS1(BASE) | S13(_off) | RD(DEST); \
204 #define emit_load8(BASE, STRUCT, FIELD, DEST) \
206 __emit_load8(BASE, STRUC
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 51 #define BASE(seg) BASE_INNER(seg) macro
54 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 47 #define BASE(seg) BASE_INNER(seg) macro
50 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 56 #define BASE(seg) BASE_INNER(seg) macro
59 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_smu.c | 51 #define BASE(seg) BASE_INNER(seg) macro
53 #define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 93 #define BASE(seg) BASE_INNER(seg) macro
96 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_smu.c | 51 #define BASE(seg) BASE_INNER(seg) macro
53 #define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_panel_cntl.h | 46 .reg_name = BASE(mm ## block ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_dwb.h | 31 #define BASE(seg) \ macro
35 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
39 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
44 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_mpc.h | 39 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| /linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
| H A D | hw_factory_dcn20.c | 55 #define BASE(seg) BASE_INNER(seg) macro
60 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
66 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
|
| H A D | hw_translate_dcn20.c | 52 #define BASE(seg) BASE_INNER(seg) macro
56 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
|
| /linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
| H A D | hw_factory_dcn21.c | 53 #define BASE(seg) BASE_INNER(seg) macro
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
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| H A D | hw_translate_dcn21.c | 52 #define BASE(seg) BASE_INNER(seg) macro
56 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
|