Searched refs:writeq_relaxed (Results 1 - 25 of 46) sorted by relevance

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/linux-master/arch/arm64/include/asm/
H A Darch_gicv3.h144 #define gic_write_irouter(v, c) writeq_relaxed(v, c)
146 #define gic_write_lpir(v, c) writeq_relaxed(v, c)
152 #define gits_write_baser(v, c) writeq_relaxed(v, c)
155 #define gits_write_cbaser(v, c) writeq_relaxed(v, c)
157 #define gits_write_cwriter(v, c) writeq_relaxed(v, c)
160 #define gicr_write_propbaser(v, c) writeq_relaxed(v, c)
162 #define gicr_write_pendbaser(v, c) writeq_relaxed(v, c)
165 #define gicr_write_vpropbaser(v, c) writeq_relaxed(v, c)
168 #define gicr_write_vpendbaser(v, c) writeq_relaxed(v, c)
/linux-master/drivers/net/ethernet/cavium/thunder/
H A Dthunder_xcv.c72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);
87 writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL);
94 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);
102 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);
106 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);
130 writeq_relaxed(cfg, xcv->reg_base + XCV_CTL);
135 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);
140 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);
143 writeq_relaxed(
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H A Dnic_main.c81 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
90 writeq_relaxed(val, nic->reg_base + offset);
146 writeq_relaxed(msg[0], mbx_addr);
147 writeq_relaxed(msg[1], mbx_addr + 8);
149 writeq_relaxed(msg[1], mbx_addr + 8);
150 writeq_relaxed(msg[0], mbx_addr);
/linux-master/include/linux/
H A Dio-64-nonatomic-hi-lo.h54 #ifndef writeq_relaxed
55 #define writeq_relaxed hi_lo_writeq_relaxed macro
H A Dio-64-nonatomic-lo-hi.h54 #ifndef writeq_relaxed
55 #define writeq_relaxed lo_hi_writeq_relaxed macro
/linux-master/arch/arm64/kernel/
H A Dsmp_spin_table.c92 writeq_relaxed(pa_holding_pen, release_addr);
H A Dacpi_parking_protocol.c102 writeq_relaxed(__pa_symbol(secondary_entry),
/linux-master/drivers/perf/
H A Dmarvell_cn10k_ddr_pmu.c374 writeq_relaxed(val, pmu->base + reg);
388 writeq_relaxed(val, pmu->base + DDRC_PERF_CNT_FREERUN_EN);
462 writeq_relaxed(val, pmu->base + reg_offset);
470 writeq_relaxed(val, pmu->base + DDRC_PERF_CNT_FREERUN_CTRL);
516 writeq_relaxed(START_OP_CTRL_VAL_START, ddr_pmu->base +
524 writeq_relaxed(END_OP_CTRL_VAL_END, ddr_pmu->base +
654 writeq_relaxed(OP_MODE_CTRL_VAL_MANNUAL, ddr_pmu->base +
H A Dmarvell_cn10k_tad_pmu.c71 writeq_relaxed(0, tad_pmu->regions[i].base +
92 writeq_relaxed(0, tad_pmu->regions[i].base +
100 writeq_relaxed(reg_val, tad_pmu->regions[i].base +
H A Darm_smmuv3_pmu.c731 writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);
743 writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);
782 writeq_relaxed(counter_present_mask,
784 writeq_relaxed(counter_present_mask,
786 writeq_relaxed(counter_present_mask,
H A Darm-cmn.c1416 writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR);
1503 writeq_relaxed(le64_to_cpu(dn->event_sel_w), dn->pmu_base + CMN_PMU_EVENT_SEL);
1520 writeq_relaxed(CMN_CC_INIT, cmn->dtc[i].base + CMN_DT_PMCCNTR);
1530 writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx));
1531 writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx));
1558 writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx));
1559 writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx));
1874 writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG);
2040 writeq_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG);
2043 writeq_relaxed(
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/linux-master/arch/mips/loongson64/
H A Dsmp.c144 writeq_relaxed(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
160 writeq_relaxed(startargs[3],
162 writeq_relaxed(startargs[2],
164 writeq_relaxed(startargs[1],
166 writeq_relaxed(startargs[0],
/linux-master/drivers/bus/fsl-mc/
H A Dmc-sys.c109 writeq_relaxed(le64_to_cpu(cmd->params[i]), &portal->params[i]);
/linux-master/drivers/crypto/marvell/octeontx2/
H A Dotx2_cpt_common.h135 writeq_relaxed(val, reg_base +
/linux-master/drivers/soc/apple/
H A Dmailbox.c153 writeq_relaxed(msg.msg0, mbox->regs + mbox->hw->a2i_send0);
154 writeq_relaxed(FIELD_PREP(APPLE_MBOX_MSG1_MSG, msg.msg1),
/linux-master/arch/sh/include/asm/
H A Dio.h47 #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)ioswabq(v),c)) macro
57 #define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); })
/linux-master/drivers/hwtracing/intel_th/
H A Dsth.c45 writeq_relaxed(*(u64 *)payload, dest);
/linux-master/include/asm-generic/
H A Dio.h384 #if defined(writeq) && !defined(writeq_relaxed)
385 #define writeq_relaxed writeq_relaxed macro
386 static inline void writeq_relaxed(u64 value, volatile void __iomem *addr) function
/linux-master/arch/x86/include/asm/
H A Dio.h100 #define writeq_relaxed(v, a) __writeq(v, a) macro
/linux-master/arch/riscv/include/asm/
H A Dmmio.h125 #define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); }) macro
/linux-master/drivers/clocksource/
H A Dtimer-clint.c118 writeq_relaxed(clint_get_cycles64() + delta, r);
/linux-master/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-nvidia.c93 writeq_relaxed(val, reg);
/linux-master/drivers/cpufreq/
H A Dapple-soc-cpufreq.c156 writeq_relaxed(reg, priv->reg_base + APPLE_DVFS_CMD);
/linux-master/drivers/mmc/host/
H A Ddw_mmc.h491 writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
/linux-master/arch/sparc/include/asm/
H A Dio_64.h187 #define writeq_relaxed writeq macro

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