1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef __ASM_SH_IO_H 3#define __ASM_SH_IO_H 4 5/* 6 * Convention: 7 * read{b,w,l,q}/write{b,w,l,q} are for PCI, 8 * while in{b,w,l}/out{b,w,l} are for ISA 9 * 10 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p 11 * and 'string' versions: ins{b,w,l}/outs{b,w,l} 12 * 13 * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers 14 * automatically, there are also __raw versions, which do not. 15 */ 16#include <linux/errno.h> 17#include <asm/cache.h> 18#include <asm/addrspace.h> 19#include <asm/machvec.h> 20#include <asm/page.h> 21#include <linux/pgtable.h> 22#include <asm-generic/iomap.h> 23 24#define __IO_PREFIX generic 25#include <asm/io_generic.h> 26#include <asm-generic/pci_iomap.h> 27#include <mach/mangle-port.h> 28 29#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v)) 30#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v)) 31#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v)) 32#define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v)) 33 34#define __raw_readb(a) (__chk_io_ptr(a), *(volatile u8 __force *)(a)) 35#define __raw_readw(a) (__chk_io_ptr(a), *(volatile u16 __force *)(a)) 36#define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a)) 37#define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a)) 38 39#define readb_relaxed(c) ({ u8 __v = ioswabb(__raw_readb(c)); __v; }) 40#define readw_relaxed(c) ({ u16 __v = ioswabw(__raw_readw(c)); __v; }) 41#define readl_relaxed(c) ({ u32 __v = ioswabl(__raw_readl(c)); __v; }) 42#define readq_relaxed(c) ({ u64 __v = ioswabq(__raw_readq(c)); __v; }) 43 44#define writeb_relaxed(v,c) ((void)__raw_writeb((__force u8)ioswabb(v),c)) 45#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)ioswabw(v),c)) 46#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c)) 47#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)ioswabq(v),c)) 48 49#define readb(a) ({ u8 r_ = readb_relaxed(a); rmb(); r_; }) 50#define readw(a) ({ u16 r_ = readw_relaxed(a); rmb(); r_; }) 51#define readl(a) ({ u32 r_ = readl_relaxed(a); rmb(); r_; }) 52#define readq(a) ({ u64 r_ = readq_relaxed(a); rmb(); r_; }) 53 54#define writeb(v,a) ({ wmb(); writeb_relaxed((v),(a)); }) 55#define writew(v,a) ({ wmb(); writew_relaxed((v),(a)); }) 56#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); }) 57#define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); }) 58 59#define readsb(p,d,l) __raw_readsb(p,d,l) 60#define readsw(p,d,l) __raw_readsw(p,d,l) 61#define readsl(p,d,l) __raw_readsl(p,d,l) 62 63#define writesb(p,d,l) __raw_writesb(p,d,l) 64#define writesw(p,d,l) __raw_writesw(p,d,l) 65#define writesl(p,d,l) __raw_writesl(p,d,l) 66 67#define __BUILD_UNCACHED_IO(bwlq, type) \ 68static inline type read##bwlq##_uncached(unsigned long addr) \ 69{ \ 70 type ret; \ 71 jump_to_uncached(); \ 72 ret = __raw_read##bwlq(addr); \ 73 back_to_cached(); \ 74 return ret; \ 75} \ 76 \ 77static inline void write##bwlq##_uncached(type v, unsigned long addr) \ 78{ \ 79 jump_to_uncached(); \ 80 __raw_write##bwlq(v, addr); \ 81 back_to_cached(); \ 82} 83 84__BUILD_UNCACHED_IO(b, u8) 85__BUILD_UNCACHED_IO(w, u16) 86__BUILD_UNCACHED_IO(l, u32) 87__BUILD_UNCACHED_IO(q, u64) 88 89#define __BUILD_MEMORY_STRING(pfx, bwlq, type) \ 90 \ 91static inline void \ 92pfx##writes##bwlq(volatile void __iomem *mem, const void *addr, \ 93 unsigned int count) \ 94{ \ 95 const volatile type *__addr = addr; \ 96 \ 97 while (count--) { \ 98 __raw_write##bwlq(*__addr, mem); \ 99 __addr++; \ 100 } \ 101} \ 102 \ 103static inline void pfx##reads##bwlq(volatile void __iomem *mem, \ 104 void *addr, unsigned int count) \ 105{ \ 106 volatile type *__addr = addr; \ 107 \ 108 while (count--) { \ 109 *__addr = __raw_read##bwlq(mem); \ 110 __addr++; \ 111 } \ 112} 113 114__BUILD_MEMORY_STRING(__raw_, b, u8) 115__BUILD_MEMORY_STRING(__raw_, w, u16) 116 117void __raw_writesl(void __iomem *addr, const void *data, int longlen); 118void __raw_readsl(const void __iomem *addr, void *data, int longlen); 119 120__BUILD_MEMORY_STRING(__raw_, q, u64) 121 122#define ioport_map ioport_map 123#define ioport_unmap ioport_unmap 124#define pci_iounmap pci_iounmap 125 126#define ioread8 ioread8 127#define ioread16 ioread16 128#define ioread16be ioread16be 129#define ioread32 ioread32 130#define ioread32be ioread32be 131 132#define iowrite8 iowrite8 133#define iowrite16 iowrite16 134#define iowrite16be iowrite16be 135#define iowrite32 iowrite32 136#define iowrite32be iowrite32be 137 138#define ioread8_rep ioread8_rep 139#define ioread16_rep ioread16_rep 140#define ioread32_rep ioread32_rep 141 142#define iowrite8_rep iowrite8_rep 143#define iowrite16_rep iowrite16_rep 144#define iowrite32_rep iowrite32_rep 145 146#ifdef CONFIG_HAS_IOPORT_MAP 147 148/* 149 * Slowdown I/O port space accesses for antique hardware. 150 */ 151#undef CONF_SLOWDOWN_IO 152 153/* 154 * On SuperH I/O ports are memory mapped, so we access them using normal 155 * load/store instructions. sh_io_port_base is the virtual address to 156 * which all ports are being mapped. 157 */ 158extern unsigned long sh_io_port_base; 159 160static inline void __set_io_port_base(unsigned long pbase) 161{ 162 *(unsigned long *)&sh_io_port_base = pbase; 163 barrier(); 164} 165 166#ifdef CONFIG_GENERIC_IOMAP 167#define __ioport_map ioport_map 168#else 169extern void __iomem *__ioport_map(unsigned long addr, unsigned int size); 170#endif 171 172#ifdef CONF_SLOWDOWN_IO 173#define SLOW_DOWN_IO __raw_readw(sh_io_port_base) 174#else 175#define SLOW_DOWN_IO 176#endif 177 178#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \ 179 \ 180static inline void pfx##out##bwlq##p(type val, unsigned long port) \ 181{ \ 182 volatile type *__addr; \ 183 \ 184 __addr = (void __iomem *)sh_io_port_base + port; \ 185 *__addr = val; \ 186 slow; \ 187} \ 188 \ 189static inline type pfx##in##bwlq##p(unsigned long port) \ 190{ \ 191 volatile type *__addr; \ 192 type __val; \ 193 \ 194 __addr = (void __iomem *)sh_io_port_base + port; \ 195 __val = *__addr; \ 196 slow; \ 197 \ 198 return __val; \ 199} 200 201#define __BUILD_IOPORT_PFX(bus, bwlq, type) \ 202 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \ 203 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO) 204 205#define BUILDIO_IOPORT(bwlq, type) \ 206 __BUILD_IOPORT_PFX(, bwlq, type) 207 208BUILDIO_IOPORT(b, u8) 209BUILDIO_IOPORT(w, u16) 210BUILDIO_IOPORT(l, u32) 211BUILDIO_IOPORT(q, u64) 212 213#define __BUILD_IOPORT_STRING(bwlq, type) \ 214 \ 215static inline void outs##bwlq(unsigned long port, const void *addr, \ 216 unsigned int count) \ 217{ \ 218 const volatile type *__addr = addr; \ 219 \ 220 while (count--) { \ 221 out##bwlq(*__addr, port); \ 222 __addr++; \ 223 } \ 224} \ 225 \ 226static inline void ins##bwlq(unsigned long port, void *addr, \ 227 unsigned int count) \ 228{ \ 229 volatile type *__addr = addr; \ 230 \ 231 while (count--) { \ 232 *__addr = in##bwlq(port); \ 233 __addr++; \ 234 } \ 235} 236 237__BUILD_IOPORT_STRING(b, u8) 238__BUILD_IOPORT_STRING(w, u16) 239__BUILD_IOPORT_STRING(l, u32) 240__BUILD_IOPORT_STRING(q, u64) 241 242#else /* !CONFIG_HAS_IOPORT_MAP */ 243 244#include <asm/io_noioport.h> 245 246#endif 247 248#define inb(addr) inb(addr) 249#define inw(addr) inw(addr) 250#define inl(addr) inl(addr) 251#define outb(x, addr) outb((x), (addr)) 252#define outw(x, addr) outw((x), (addr)) 253#define outl(x, addr) outl((x), (addr)) 254 255#define inb_p(addr) inb(addr) 256#define inw_p(addr) inw(addr) 257#define inl_p(addr) inl(addr) 258#define outb_p(x, addr) outb((x), (addr)) 259#define outw_p(x, addr) outw((x), (addr)) 260#define outl_p(x, addr) outl((x), (addr)) 261 262#define insb insb 263#define insw insw 264#define insl insl 265#define outsb outsb 266#define outsw outsw 267#define outsl outsl 268 269#define IO_SPACE_LIMIT 0xffffffff 270 271/* We really want to try and get these to memcpy etc */ 272#define memset_io memset_io 273#define memcpy_fromio memcpy_fromio 274#define memcpy_toio memcpy_toio 275void memcpy_fromio(void *, const volatile void __iomem *, unsigned long); 276void memcpy_toio(volatile void __iomem *, const void *, unsigned long); 277void memset_io(volatile void __iomem *, int, unsigned long); 278 279/* Quad-word real-mode I/O, don't ask.. */ 280unsigned long long peek_real_address_q(unsigned long long addr); 281unsigned long long poke_real_address_q(unsigned long long addr, 282 unsigned long long val); 283 284#if !defined(CONFIG_MMU) 285#define virt_to_phys(address) ((unsigned long)(address)) 286#define phys_to_virt(address) ((void *)(address)) 287#else 288#define virt_to_phys(address) (__pa(address)) 289#define phys_to_virt(address) (__va(address)) 290#endif 291 292#ifdef CONFIG_MMU 293/* 294 * I/O memory mapping functions. 295 */ 296#define ioremap_prot ioremap_prot 297#define iounmap iounmap 298 299#define _PAGE_IOREMAP pgprot_val(PAGE_KERNEL_NOCACHE) 300 301#define ioremap_cache(addr, size) \ 302 ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL)) 303#endif /* CONFIG_MMU */ 304 305#include <asm-generic/io.h> 306 307#define ARCH_HAS_VALID_PHYS_ADDR_RANGE 308int valid_phys_addr_range(phys_addr_t addr, size_t size); 309int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); 310 311#endif /* __ASM_SH_IO_H */ 312