Searched refs:writel (Results 1 - 25 of 2418) sorted by relevance

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/linux-master/arch/arc/plat-hsdk/
H A Dplatform.c209 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
210 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
211 writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_0));
212 writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_0));
213 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
215 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
216 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
217 writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_1));
218 writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_1));
219 writel(UPDATE_VA
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/linux-master/arch/arm/mach-shmobile/
H A Dsetup-r8a7779.c37 writel(0xffffffff, base + INT2NTSR0);
38 writel(0x3fffffff, base + INT2NTSR1);
41 writel(0xfffffff0, base + INT2SMSKCR0);
42 writel(0xfff7ffff, base + INT2SMSKCR1);
43 writel(0xfffbffdf, base + INT2SMSKCR2);
44 writel(0xbffffffc, base + INT2SMSKCR3);
45 writel(0x003fee3f, base + INT2SMSKCR4);
H A Dsetup-r8a7778.c34 writel(0x73ffffff, base + INT2NTSR0);
35 writel(0xffffffff, base + INT2NTSR1);
38 writel(0x08330773, base + INT2SMSKCR0);
39 writel(0x00311110, base + INT2SMSKCR1);
/linux-master/drivers/media/platform/samsung/s5p-jpeg/
H A Djpeg-hw-exynos3250.c23 writel(1, regs + EXYNOS3250_SW_RESET);
35 writel(1, regs + EXYNOS3250_JPGDRI);
41 writel(0, regs + EXYNOS3250_JPGDRI);
46 writel(EXYNOS3250_POWER_ON, regs + EXYNOS3250_JPGCLKCON);
51 writel(((EXYNOS3250_DMA_MO_COUNT << EXYNOS3250_WDMA_ISSUE_NUM_SHIFT) &
66 writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD);
117 writel(reg, regs + EXYNOS3250_JPGCMOD);
129 writel(reg, regs + EXYNOS3250_JPGCMOD);
143 writel(reg, regs + EXYNOS3250_JPGMOD);
165 writel(re
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H A Djpeg-hw-exynos4.c21 writel(reg & ~(EXYNOS4_DEC_MODE | EXYNOS4_ENC_MODE),
25 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG);
29 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG);
39 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) |
43 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) |
47 writel(reg & EXYNOS4_ENC_DEC_MODE_MASK,
133 writel(reg, base + EXYNOS4_IMG_FMT_REG);
166 writel(reg, base + EXYNOS4_IMG_FMT_REG);
175 writel(reg | EXYNOS4_INT_EN_ALL, base + EXYNOS4_INT_EN_REG);
179 writel(re
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/linux-master/drivers/video/fbdev/
H A Dwmt_ge_rops.c62 writel(p->var.bits_per_pixel == 32 ? 3 :
64 writel(p->var.bits_per_pixel == 15 ? 1 : 0, regbase + GE_HIGHCOLOR_OFF);
65 writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF);
66 writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF);
67 writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF);
68 writel(rect->dx, regbase + GE_DESTAREAX_OFF);
69 writel(rect->dy, regbase + GE_DESTAREAY_OFF);
70 writel(rect->width - 1, regbase + GE_DESTAREAW_OFF);
71 writel(rect->height - 1, regbase + GE_DESTAREAH_OFF);
73 writel(pa
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/linux-master/drivers/net/ethernet/chelsio/cxgb/
H A Dtp.c32 writel(val, ap->regs + A_TP_IN_CONFIG);
33 writel(F_TP_OUT_CSPI_CPL |
37 writel(V_IP_TTL(64) |
47 writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR |
78 writel(0xffffffff,
80 writel(tp_intr | FPGA_PCIX_INTERRUPT_TP,
86 writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
87 writel(tp_intr | F_PL_INTR_TP,
99 writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE);
100 writel(tp_int
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H A Despi.c56 writel(V_WRITE_DATA(wr_data) |
62 writel(0, adapter->regs + A_ESPI_GOSTAT);
83 writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET);
102 writel(F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST,
120 writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE);
121 writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);
127 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS);
128 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE);
135 writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE);
136 writel(pl_int
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/linux-master/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_reg.c33 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
37 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
47 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
61 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
69 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1);
72 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
79 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
80 writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
81 writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
82 writel(
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/linux-master/drivers/ata/
H A Dahci_qoriq.c134 writel(px_cmd, port_mmio + PORT_CMD);
138 writel(px_is, port_mmio + PORT_IRQ_STAT);
174 writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
175 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
176 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
177 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
178 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
179 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
180 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
182 writel(AHCI_PORT_AXICC_CF
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/linux-master/arch/arm/mach-s3c/
H A Dsetup-usb-phy-s3c64xx.c28 writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
51 writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK);
54 writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR);
58 writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK,
61 writel(0, S3C_RSTCON);
68 writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN |
71 writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
/linux-master/drivers/video/fbdev/via/
H A Daccel.c34 writel(gemode, engine + VIA_REG_GEMODE);
91 writel(tmp, engine + 0x08);
100 writel(tmp, engine + 0x0C);
108 writel(tmp, engine + 0x10);
111 writel(fg_color, engine + 0x18);
114 writel(bg_color, engine + 0x1C);
124 writel(tmp, engine + 0x30);
133 writel(tmp, engine + 0x34);
145 writel(tmp, engine + 0x38);
158 writel(ge_cm
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/linux-master/drivers/phy/qualcomm/
H A Dphy-qcom-edp.c189 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
194 writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
196 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL);
199 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
209 writel(0xfc, edp->edp + DP_PHY_MODE);
211 writel(0x00, edp->edp + DP_PHY_AUX_CFG0);
212 writel(0x13, edp->edp + DP_PHY_AUX_CFG1);
213 writel(0x24, edp->edp + DP_PHY_AUX_CFG2);
214 writel(0x00, edp->edp + DP_PHY_AUX_CFG3);
215 writel(
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/linux-master/arch/arm/plat-orion/
H A Dtime.c87 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
91 writel(u, bridge_base + BRIDGE_MASK_OFF);
96 writel(delta, timer_base + TIMER1_VAL_OFF);
103 writel(u, timer_base + TIMER_CTRL_OFF);
119 writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
123 writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
126 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
141 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
142 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
146 writel(
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H A Dpcie.c89 writel(stat, base + PCIE_STAT_OFF);
105 writel(reg, base + PCIE_DEBUG_CTRL);
115 writel(reg, base + PCIE_DEBUG_CTRL);
135 writel(0, base + PCIE_BAR_CTRL_OFF(i));
136 writel(0, base + PCIE_BAR_LO_OFF(i));
137 writel(0, base + PCIE_BAR_HI_OFF(i));
141 writel(0, base + PCIE_WIN04_CTRL_OFF(i));
142 writel(0, base + PCIE_WIN04_BASE_OFF(i));
143 writel(0, base + PCIE_WIN04_REMAP_OFF(i));
146 writel(
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/linux-master/arch/arm/mach-rockchip/
H A Drockchip.c34 writel(0, reg_base + 0x30);
35 writel(0xffffffff, reg_base + 0x20);
36 writel(0xffffffff, reg_base + 0x24);
37 writel(1, reg_base + 0x30);
/linux-master/arch/arm/mach-socfpga/
H A Dl2_cache.c42 writel(0x01, mapped_l2_edac_addr);
70 writel(A10_SYSMGR_MPU_CLEAR_L2_ECC, (sys_manager_base_addr +
73 writel(A10_SYSMGR_ECC_INTMASK_CLR_L2, sys_manager_base_addr +
75 writel(A10_MPU_CTRL_L2_ECC_EN, mapped_l2_edac_addr +
/linux-master/sound/soc/sunxi/
H A Dsun8i-adda-pr-regmap.c35 writel(readl(base) | ADDA_PR_RESET, base);
38 writel(readl(base) & ~ADDA_PR_WRITE, base);
44 writel(tmp, base);
58 writel(readl(base) | ADDA_PR_RESET, base);
64 writel(tmp, base);
70 writel(tmp, base);
73 writel(readl(base) | ADDA_PR_WRITE, base);
76 writel(readl(base) & ~ADDA_PR_WRITE, base);
/linux-master/arch/arm/mach-orion5x/
H A Dtsx09-common.c32 writel(0x83, UART1_REG(LCR));
33 writel(divisor & 0xff, UART1_REG(DLL));
34 writel((divisor >> 8) & 0xff, UART1_REG(DLM));
35 writel(0x03, UART1_REG(LCR));
36 writel(0x00, UART1_REG(IER));
37 writel(0x00, UART1_REG(FCR));
38 writel(0x00, UART1_REG(MCR));
41 writel('A', UART1_REG(TX));
/linux-master/sound/soc/pxa/
H A Dpxa2xx-i2s.c103 writel(0, i2s_reg_base + SACR0);
175 writel(0, i2s_reg_base + SACR0);
177 writel(readl(i2s_reg_base + SACR0) | (SACR0_BCKD), i2s_reg_base + SACR0);
179 writel(readl(i2s_reg_base + SACR0) | (SACR0_RFTH(14) | SACR0_TFTH(1)), i2s_reg_base + SACR0);
180 writel(readl(i2s_reg_base + SACR1) | (pxa_i2s.fmt), i2s_reg_base + SACR1);
183 writel(readl(i2s_reg_base + SAIMR) | (SAIMR_TFS), i2s_reg_base + SAIMR);
185 writel(readl(i2s_reg_base + SAIMR) | (SAIMR_RFS), i2s_reg_base + SAIMR);
189 writel(0x48, i2s_reg_base + SADIV);
192 writel(0x34, i2s_reg_base + SADIV);
195 writel(
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/linux-master/drivers/net/ethernet/sunplus/
H A Dspl2sw_mac.c22 writel(0xffffffff, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);
23 writel(0xffffffff, comm->l2sw_reg_base + L2SW_SW_INT_STATUS_0);
28 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL);
34 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0);
45 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL);
50 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0);
60 writel((mac->mac_addr[0] << 0) + (mac->mac_addr[1] << 8),
62 writel((mac->mac_addr[2] << 0) + (mac->mac_addr[3] << 8) +
69 writel(reg, comm->l2sw_reg_base + L2SW_WT_MAC_AD0);
95 writel((ma
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/linux-master/sound/soc/ux500/
H A Dux500_msp_i2s.c138 writel(temp_reg, msp->registers + MSP_TCF);
166 writel(temp_reg, msp->registers + MSP_RCF);
205 writel(temp_reg, msp->registers + MSP_GCR);
208 writel(temp_reg, msp->registers + MSP_GCR);
223 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR);
255 writel(temp_reg, msp->registers + MSP_SRG);
262 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR);
292 writel(reg_val_MCR | (mcfg->tx_multichannel_enable ?
295 writel(mcfg->tx_channel_0_enable,
297 writel(mcf
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/linux-master/drivers/scsi/bfa/
H A Dbfa_ioc_ct.c66 writel(1, ioc->ioc_regs.ioc_usage_reg);
68 writel(1, ioc->ioc_regs.ioc_usage_sem_reg);
69 writel(0, ioc->ioc_regs.ioc_fail_sync);
88 writel(1, ioc->ioc_regs.ioc_usage_sem_reg);
97 writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
99 writel(1, ioc->ioc_regs.ioc_usage_sem_reg);
117 writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
121 writel(1, ioc->ioc_regs.ioc_usage_sem_reg);
131 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt);
132 writel(__FW_INIT_HALT_
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/linux-master/drivers/video/fbdev/geode/
H A Ddisplay_gx1.c86 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
93 writel(tcfg, par->dc_regs + DC_TIMING_CFG);
100 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
104 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
110 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
131 writel(0, par->dc_regs + DC_FB_ST_OFFSET);
134 writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA);
135 writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,
162 writel(val, par->dc_regs + DC_H_TIMING_1);
164 writel(va
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/linux-master/drivers/irqchip/
H A Dirq-sun4i.c56 writel(BIT(0), irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));
68 writel(val & ~(1 << irq_off),
81 writel(val | (1 << irq_off),
116 writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 0));
117 writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 1));
118 writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(irq_ic_data, 2));
121 writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 0));
122 writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 1));
123 writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(irq_ic_data, 2));
126 writel(
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Completed in 209 milliseconds

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