Searched refs:wb_info (Results 1 - 10 of 10) sorted by relevance
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
H A D | dcn30_hwseq.h | 40 struct dc_writeback_info *wb_info, 44 struct dc_writeback_info *wb_info, 53 struct dc_writeback_info *wb_info);
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H A D | dcn30_hwseq.c | 409 struct dc_writeback_info *wb_info, 415 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 416 ASSERT(wb_info->wb_enabled); 417 ASSERT(wb_info->mpcc_inst >= 0); 418 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); 419 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 420 mcif_buf_params = &wb_info->mcif_buf_params; 424 wb_info->dwb_pipe_inst, wb_info->mpcc_inst); 426 mcif_wb->funcs->config_mcif_buf(mcif_wb, mcif_buf_params, wb_info 407 dcn30_set_writeback( struct dc *dc, struct dc_writeback_info *wb_info, struct dc_state *context) argument 430 dcn30_update_writeback( struct dc *dc, struct dc_writeback_info *wb_info, struct dc_state *context) argument 447 dcn30_mmhubbub_warmup( struct dc *dc, unsigned int num_dwb, struct dc_writeback_info *wb_info) argument 505 dcn30_enable_writeback( struct dc *dc, struct dc_writeback_info *wb_info, struct dc_state *context) argument 558 struct dc_writeback_info wb_info; local [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
H A D | dcn30_fpu.c | 278 struct dc_writeback_info *wb_info = &stream->writeback_info[j]; local 280 if (wb_info->wb_enabled && wb_info->writeback_source_plane && 281 (wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) { 284 dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ? 285 wb_info->dwb_params.cnv_params.crop_height : 286 wb_info->dwb_params.cnv_params.src_height; 287 dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ? 288 wb_info->dwb_params.cnv_params.crop_width : 289 wb_info [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/core/ |
H A D | dc_stream.c | 405 struct dc_writeback_info *wb_info) 416 if (wb_info == NULL) { 421 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) { 428 wb_info->dwb_params.out_transfer_func = stream->out_transfer_func; 430 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 438 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) { 439 stream->writeback_info[i] = *wb_info; 446 stream->writeback_info[stream->num_wb_info++] = *wb_info; 451 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 463 struct dwbc *dwb = dc->res_pool->dwbc[wb_info 403 dc_stream_add_writeback(struct dc *dc, struct dc_stream_state *stream, struct dc_writeback_info *wb_info) argument 562 dc_stream_warmup_writeback(struct dc *dc, int num_dwb, struct dc_writeback_info *wb_info) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
H A D | dcn20_fpu.c | 999 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0]; local 1005 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; 1007 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; 1008 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; 1009 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; 1010 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; 1013 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; 1014 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c; 1017 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) { 1018 if (wb_info 2492 struct dc_writeback_info *wb_info = &stream->writeback_info[j]; local [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/ |
H A D | hw_sequencer.h | 310 struct dc_writeback_info *wb_info, 313 struct dc_writeback_info *wb_info, 320 struct dc_writeback_info *wb_info);
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
H A D | dcn20_hwseq.h | 116 struct dc_writeback_info *wb_info,
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H A D | dcn20_hwseq.c | 2409 struct dc_writeback_info *wb_info, 2416 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); 2417 ASSERT(wb_info->wb_enabled); 2418 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; 2419 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; 2423 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); 2425 mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height); 2426 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); 2430 dwb->funcs->enable(dwb, &wb_info 2407 dcn20_enable_writeback( struct dc *dc, struct dc_writeback_info *wb_info, struct dc_state *context) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/ |
H A D | dc_stream.h | 404 struct dc_writeback_info *wb_info); 420 struct dc_writeback_info *wb_info);
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/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm.c | 9034 struct dc_writeback_info *wb_info; local 9039 wb_info = kzalloc(sizeof(*wb_info), GFP_KERNEL); 9040 if (!wb_info) { 9041 DRM_ERROR("Failed to allocate wb_info\n"); 9048 kfree(wb_info); 9055 kfree(wb_info); 9066 /* fill in wb_info */ 9067 wb_info->wb_enabled = true; 9069 wb_info [all...] |
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