/linux-master/sound/pci/emu10k1/ |
H A D | emu10k1.c | 75 struct snd_seq_device *wave = NULL; local 150 sizeof(struct snd_emu10k1_synth_arg), &wave) < 0 || 151 wave == NULL) { 156 arg = SNDRV_SEQ_DEVICE_ARGPTR(wave); 157 strcpy(wave->name, "Emu-10k1 Synth");
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/linux-master/sound/pci/au88x0/ |
H A D | au88x0.c | 267 sizeof(snd_vortex_synth_arg_t), &wave) < 0 268 || wave == NULL) { 273 arg = SNDRV_SEQ_DEVICE_ARGPTR(wave); 274 strcpy(wave->name, "Aureal Synth");
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/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_umr.h | 50 u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id; member in struct:amdgpu_debugfs_gprwave_iocdata
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H A D | gfx_v9_4_2.c | 422 uint32_t se, cu, simd, wave; local 431 dev_dbg(adev->dev, "wave assignment:\n"); 439 for (wave = 0; wave < WAVE_ID_MAX; wave++) { 456 uint32_t se, cu, simd, wave; local 468 for (wave = 0; wave < WAVE_ID_MAX; wave++) { 469 if (((1 << wave) 1804 wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) argument 1818 uint32_t i, simd, wave; local [all...] |
H A D | amdgpu_gfx.h | 283 uint32_t wave, uint32_t *dst, int *no_fields); 285 uint32_t wave, uint32_t thread, uint32_t start, 288 uint32_t wave, uint32_t start, uint32_t size,
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H A D | gfx_v6_0.c | 2946 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) argument 2949 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2957 uint32_t wave, uint32_t thread, 2961 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2971 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) argument 2973 /* type 0 wave data */ 2975 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 2976 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 2977 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 2978 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_L 2956 wave_read_regs(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t regno, uint32_t num, uint32_t *out) argument 2996 gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst) argument [all...] |
H A D | gfx_v9_4_3.c | 556 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) argument 559 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 567 uint32_t wave, uint32_t thread, 571 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 582 uint32_t xcc_id, uint32_t simd, uint32_t wave, 585 /* type 1 wave data */ 587 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 588 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 589 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 590 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_L 566 wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t regno, uint32_t num, uint32_t *out) argument 581 gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) argument 604 gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst) argument 612 gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst) argument [all...] |
H A D | amdgpu_debugfs.c | 434 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x); 439 adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread, *pos, size>>2, data); 442 adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, data); 1041 * The offset being sought changes which wave that the status data 1061 uint32_t offset, se, sh, cu, wave, simd, data[32]; local 1071 wave = (*pos & GENMASK_ULL(36, 31)) >> 31; 1092 adev->gfx.funcs->read_wave_data(adev, 0, simd, wave, data, &x); 1125 /** amdgpu_debugfs_gpr_read - Read wave gprs 1132 * The offset being sought changes which wave that the status data 1153 uint32_t offset, se, sh, cu, wave, sim local [all...] |
H A D | gfx_v7_0.c | 2234 /* Currently, there is a high possibility to get wave ID mismatch 2236 * different wave IDs than the GDS expects. This situation happens 2238 * The wave IDs generated by ME are also wrong after suspend/resume. 2241 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 4087 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) argument 4090 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4098 uint32_t wave, uint32_t thread, 4102 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4112 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) argument 4114 /* type 0 wave dat 4097 wave_read_regs(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t regno, uint32_t num, uint32_t *out) argument 4137 gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst) argument [all...] |
H A D | gfx_v8_0.c | 5192 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) argument 5195 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 5203 uint32_t wave, uint32_t thread, 5207 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 5217 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) argument 5219 /* type 0 wave data */ 5221 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 5222 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 5223 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 5224 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_L 5202 wave_read_regs(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t regno, uint32_t num, uint32_t *out) argument 5242 gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst) argument [all...] |
H A D | gfx_v9_0.c | 1742 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) argument 1745 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1753 uint32_t wave, uint32_t thread, 1757 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1767 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) argument 1769 /* type 1 wave data */ 1771 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 1772 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 1773 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 1774 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_L 1752 wave_read_regs(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t regno, uint32_t num, uint32_t *out) argument 1788 gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst) argument 1797 gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst) argument [all...] |
H A D | gfx_v11_0.c | 786 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) argument 789 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 794 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, argument 799 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 807 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) argument 814 /* type 3 wave data */ 816 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 817 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 818 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 819 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_L 833 gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst) argument 844 gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst) argument [all...] |
H A D | gfx_v10_0.c | 4259 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) argument 4262 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4267 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, argument 4272 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4280 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) argument 4288 /* type 2 wave data */ 4290 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4291 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4292 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4293 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_L 4308 gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst) argument 4319 gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst) argument [all...] |
/linux-master/sound/pci/ |
H A D | ad1889.c | 90 struct ad1889_register_state wave; member in struct:snd_ad1889 187 /* Disable wave channel */ 190 chip->wave.reg = reg; 358 chip->wave.size = size; 359 chip->wave.reg = reg; 360 chip->wave.addr = rt->dma_addr; 362 ad1889_writew(chip, AD_DS_WSMC, chip->wave.reg); 368 ad1889_load_wave_buffer_address(chip, chip->wave.addr); 379 chip->wave.addr, count, size, reg, rt->rate); 460 chip->wave [all...] |
/linux-master/drivers/gpu/drm/amd/amdkfd/ |
H A D | cwsr_trap_handler_gfx9.asm | 212 // Host trap may occur while wave is halted. 232 // and debugger (host trap, wave start/end, trap after instruction) 233 // exceptions always cause the wave to enter the trap handler. 244 // Maskable exceptions only cause the wave to enter the trap handler if 266 // Second-level trap will halt wave and RFE, re-entering for SAVECTX. 307 // If not caused by trap then halt wave to prevent re-entry. 366 s_sleep 0x2 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0 435 /* the first wave in the threadgroup */ 436 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit 438 s_or_b32 s_save_exec_hi, s_save_tmp, s_save_exec_hi // save first wave bi [all...] |
H A D | cwsr_trap_handler_gfx8.asm | 226 s_sleep 0x2 // sleep 1 (64clk) is not enough for 8 waves per SIMD, which will cause SQ hang, since the 7,8th wave could not get arbit to exec inst, while other waves are stuck into the sleep-loop and waiting for wrexec!=0 288 /* the first wave in the threadgroup */ 290 s_and_b32 s_save_tmp, s_save_spi_init_hi, S_SAVE_SPI_INIT_FIRST_WAVE_MASK // extract fisrt wave bit 291 //s_or_b32 tba_hi, s_save_tmp, tba_hi // save first wave bit to tba_hi.bits[26] 293 s_or_b32 s_save_exec_hi, s_save_tmp, s_save_exec_hi // save first wave bit to s_save_exec_hi.bits[26] 341 // each wave will alloc 4 vgprs at least... 377 // first wave do LDS save; 487 /* the first wave in the threadgroup */ 666 s_barrier //barrier to ensure the readiness of LDS before access attempts from any other wave in the same TG //FIXME not performance-optimal at this time
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H A D | cwsr_trap_handler_gfx10.asm | 222 // Host trap may occur while wave is halted. 242 // and xnack_error exceptions always cause the wave to enter the trap 248 // Maskable exceptions only cause the wave to enter the trap handler if 270 // Second-level trap will halt wave and RFE, re-entering for SAVECTX. 317 // If not caused by trap then halt wave to prevent re-entry. 375 // SQ hang, since the 7,8th wave could not get arbit to exec inst, while 657 // first wave do LDS save; 1154 s_barrier //barrier to ensure the readiness of LDS before access attemps from any other wave in the same TG
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/linux-master/drivers/gpu/ipu-v3/ |
H A D | ipu-dc.c | 120 int map, int wave, int glue, int sync, int stop) 129 reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000); 132 reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000); 119 dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand, int map, int wave, int glue, int sync, int stop) argument
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