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0ef6845c |
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06-Mar-2020 |
Jay Cornwall <jay.cornwall@amd.com> |
drm/amdkfd: Add aldebaran trap handler support Similar to arcturus, but ARCH/ACC VGPRs may now be split unevenly. A new field in SQ_WAVE_GPR_ALLOC tracks the boundary between the two sets of VGPRs. Squash below patches: drm/amdkfd: Use preprocessor for IP-specific trap handler code drm/amdkfd: Fix VGPR restore race in gfx8/gfx9 trap handler drm/amdkfd: Remove duplicated code in gfx9 trap handler drm/amdkfd: Separate ARCH/ACC VGPR restore in trap handler drm/amdkfd: Reverse order of ARCH/ACC VGPR restore in trap handler Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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306fc9c5 |
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23-Jul-2019 |
Jay Cornwall <jay.cornwall@amd.com> |
drm/amdkfd: Remove dead code from gfx8/gfx9 trap handlers Signed-off-by: Jay Cornwall <jay.cornwall@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2db2f259 |
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14-Nov-2018 |
Jay Cornwall <Jay.Cornwall@amd.com> |
drm/amdkfd: Fix gfx8 MEM_VIOL exception handler When MEM_VIOL is asserted the context save handler rewinds the program counter. This is incorrect for any source of the exception. MEM_VIOL may be raised in normal operation by out-of-bounds access to LDS or GDS and does not require special handling. Remove PC adjustment when MEM_VIOL has been raised. Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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a60d811b |
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11-Jul-2018 |
Jay Cornwall <Jay.Cornwall@amd.com> |
drm/amdkfd: Fix race between scheduler and context restore The scheduler may raise SQ_WAVE_STATUS.SPI_PRIO via SQ_CMD before context restore has completed. Restoring SPI_PRIO=0 after this point may cause context save to fail as the lower priority wavefronts are not selected for execution among spin-waiting wavefronts. Leave SPI_PRIO at its SPI-initialized or scheduler-raised value. v2: Also fix race with exception handler Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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f8ea72d0 |
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01-May-2018 |
Yong Zhao <yong.zhao@amd.com> |
drm/amdkfd: Fix CP soft hang on APUs The problem happens on Raven and Carrizo. The context save handler should not clear the high bits of PC_HI before extracting the bits of IB_STS. The bug is not relevant to VEGA10 until we enable demand paging. Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com> Signed-off-by: Yong Zhao <yong.zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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0db54b24 |
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01-May-2018 |
Yong Zhao <yong.zhao@amd.com> |
drm/amdkfd: Separate trap handler assembly code and its hex values Since the assembly code is inside "#if 0", it is ineffective. Despite that, during debugging, we need to change the assembly code, extract it into a separate file and compile the new file into hex values using sp3. That process also requires us to remove "#if 0" and modify lines starting with "#", so that sp3 can successfully compile the new file. With this change, all the above chore is no longer needed, and cwsr_trap_handler_gfx*.asm can be directly used by sp3 to generate its hex values. Signed-off-by: Yong Zhao <yong.zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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87e6d4e0 |
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01-May-2018 |
Jay Cornwall <Jay.Cornwall@amd.com> |
drm/amdkfd: Reduce priority of context-saving waves before spin-wait Synchronization between context-saving wavefronts is achieved by sending a SAVEWAVE message to the SPI and then spin-waiting for a response. These spin-waiting wavefronts may inhibit the progress of other wavefronts in the context save handler, leading to the synchronization condition never being achieved. Before spin-waiting reduce the priority of each wavefront to guarantee foward progress in the others. Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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449fea61 |
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14-Nov-2017 |
Felix Kuehling <Felix.Kuehling@amd.com> |
drm/amdkfd: Add trap handler for CWSR The trap handler is like an interrupt handler running on the GPU compute unit. It is needed for supporting CWSR (compute wave save/restore). This file defines an array with the pre-compiled GFXv8 shader ISA. The assembly code is included for reference in #if 0 ... #endif. Signed-off-by: Shaoyun.liu <shaoyun.liu@amd.com> Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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