/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/ |
H A D | dcn10_dpp_dscl.c | 450 bool dpp1_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps) argument 453 return vtaps <= (num_partitions - ceil_vratio + 2); 455 return vtaps <= num_partitions; 463 int vtaps = scl_data->taps.v_taps; local 478 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) 485 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) 494 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) 502 /*Ensure we can support the requested number of vtaps*/ 503 ASSERT(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
|
H A D | dcn10_dpp.h | 1399 int vtaps);
|
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
H A D | display_mode_vba_21.c | 163 double vtaps, 321 unsigned int vtaps[], 1214 double vtaps, 1225 *VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1); 1227 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); 1520 mode_lib->vba.vtaps[k] / 6.0 1530 if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6) 1867 mode_lib->vba.vtaps[k], 2453 mode_lib->vba.vtaps, 3542 || mode_lib->vba.vtaps[ 1211 CalculatePrefetchSourceLines( struct display_mode_lib *mode_lib, double VRatio, double vtaps, bool Interlace, bool ProgressiveToInterlaceUnitInOPP, unsigned int SwathHeight, unsigned int ViewportYStart, double *VInitPreFill, unsigned int *MaxNumSwath) argument 5242 CalculateWatermarksAndDRAMSpeedChangeSupport( struct display_mode_lib *mode_lib, unsigned int PrefetchMode, unsigned int NumberOfActivePlanes, unsigned int MaxLineBufferLines, unsigned int LineBufferSize, unsigned int DPPOutputBufferPixels, unsigned int DETBufferSizeInKByte, unsigned int WritebackInterfaceLumaBufferSize, unsigned int WritebackInterfaceChromaBufferSize, double DCFCLK, double UrgentOutOfOrderReturn, double ReturnBW, bool GPUVMEnable, int dpte_group_bytes[], unsigned int MetaChunkSize, double UrgentLatency, double ExtraLatency, double WritebackLatency, double WritebackChunkSize, double SOCCLK, double DRAMClockChangeLatency, double SRExitTime, double SREnterPlusExitTime, double DCFCLKDeepSleep, int DPPPerPlane[], bool DCCEnable[], double DPPCLK[], double SwathWidthSingleDPPY[], unsigned int SwathHeightY[], double ReadBandwidthPlaneLuma[], unsigned int SwathHeightC[], double ReadBandwidthPlaneChroma[], unsigned int LBBitPerPixel[], double SwathWidthY[], double HRatio[], unsigned int vtaps[], unsigned int VTAPsChroma[], double VRatio[], unsigned int HTotal[], double PixelClock[], unsigned int BlendingAndTiming[], double BytePerPixelDETY[], double BytePerPixelDETC[], bool WritebackEnable[], enum source_format_class WritebackPixelFormat[], double WritebackDestinationWidth[], double WritebackDestinationHeight[], double WritebackSourceHeight[], enum clock_change_support *DRAMClockChangeSupport, double *UrgentWatermark, double *WritebackUrgentWatermark, double *DRAMClockChangeWatermark, double *WritebackDRAMClockChangeWatermark, double *StutterExitWatermark, double *StutterEnterPlusExitWatermark, double *MinActiveDRAMClockChangeLatencySupported) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/ |
H A D | display_mode_lib.c | 259 dml_print("DML PARAMS: vtaps = %d\n", scale_taps->vtaps);
|
H A D | display_mode_structs.h | 502 unsigned int vtaps; member in struct:_vcs_dpi_scaler_taps_st
|
H A D | display_mode_vba.h | 468 unsigned int vtaps[DC__NUM_DPP__MAX]; member in struct:vba_vars_st
|
H A D | display_mode_vba.c | 600 mode_lib->vba.vtaps[mode_lib->vba.NumberOfActivePlanes] = taps->vtaps;
|
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
H A D | display_mode_vba_20v2.c | 149 double vtaps, 875 double vtaps, 886 *VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1); 888 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); 1196 mode_lib->vba.vtaps[k] / 6.0 1206 if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6) 1932 mode_lib->vba.vtaps[k], 2456 1)) - (mode_lib->vba.vtaps[k] - 1); 3415 || mode_lib->vba.vtaps[k] != 1.0)) { 3417 } else if (mode_lib->vba.vtaps[ 872 CalculatePrefetchSourceLines( struct display_mode_lib *mode_lib, double VRatio, double vtaps, bool Interlace, bool ProgressiveToInterlaceUnitInOPP, unsigned int SwathHeight, unsigned int ViewportYStart, double *VInitPreFill, unsigned int *MaxNumSwath) argument [all...] |
H A D | display_mode_vba_20.c | 125 double vtaps, 815 double vtaps, 826 *VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1); 828 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); 1136 mode_lib->vba.vtaps[k] / 6.0 1146 if ((mode_lib->vba.htaps[k] > 6 || mode_lib->vba.vtaps[k] > 6) 1896 mode_lib->vba.vtaps[k], 2422 1)) - (mode_lib->vba.vtaps[k] - 1); 3308 || mode_lib->vba.vtaps[k] != 1.0)) { 3310 } else if (mode_lib->vba.vtaps[ 812 CalculatePrefetchSourceLines( struct display_mode_lib *mode_lib, double VRatio, double vtaps, bool Interlace, bool ProgressiveToInterlaceUnitInOPP, unsigned int SwathHeight, unsigned int ViewportYStart, double *VInitPreFill, unsigned int *MaxNumSwath) argument [all...] |
H A D | dcn20_fpu.c | 1571 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1; 1677 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
|
/linux-master/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
H A D | dcn_calc_auto.c | 99 v->vtaps[k] = v->override_vta_ps[k]; 102 v->vtaps[k] = v->acceptable_quality_vta_ps; 132 if (v->h_ratio[k] > v->max_hscl_ratio || v->v_ratio[k] > v->max_vscl_ratio || v->h_ratio[k] > v->htaps[k] || v->v_ratio[k] > v->vtaps[k] || (v->source_pixel_format[k] != dcn_bw_rgb_sub_64 && v->source_pixel_format[k] != dcn_bw_rgb_sub_32 && v->source_pixel_format[k] != dcn_bw_rgb_sub_16 && (v->h_ratio[k] / 2.0 > v->hta_pschroma[k] || v->v_ratio[k] / 2.0 > v->vta_pschroma[k]))) { 331 v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], 1.0); 340 v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max5(v->vtaps[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k]), v->h_ratio[k] * v->v_ratio[k] / v->pscl_factor[k], v->vta_pschroma[k] / 6.0 *dcn_bw_min2(1.0, v->h_ratio[k] / 2.0), v->h_ratio[k] * v->v_ratio[k] / 4.0 / v->pscl_factor_chroma[k], 1.0); 427 v->number_of_dpp_required_for_lb_size =dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] /dcn_bw_max2(v->h_ratio[k], 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0); 430 v->number_of_dpp_required_for_lb_size =dcn_bw_max2(dcn_bw_ceil2((v->vtaps[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k], 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] /dcn_bw_max2(v->h_ratio[k], 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0),dcn_bw_ceil2((v->vta_pschroma[k] +dcn_bw_max2(dcn_bw_ceil2(v->v_ratio[k] / 2.0, 1.0) - 2, 0.0)) * v->swath_width_ysingle_dpp[k] / 2.0 /dcn_bw_max2(v->h_ratio[k] / 2.0, 1.0) * v->lb_bit_per_pixel[k] / v->line_buffer_size, 1.0)); 554 v->effective_lb_latency_hiding_source_lines_luma =dcn_bw_min2(v->max_line_buffer_lines,dcn_bw_floor2(v->line_buffer_size / v->lb_bit_per_pixel[k] / (v->swath_width_yper_state[i][j][k] /dcn_bw_max2(v->h_ratio[k], 1.0)), 1.0)) - (v->vtaps[k] - 1.0); 747 v->v_init_y = (v->v_ratio[k] + v->vtaps[k] + 1.0 + v->interlace_output[k] * 0.5 * v->v_ratio[k]) / 2.0; 759 v->v_init_c = (v->v_ratio[k] / 2.0 + v->vtaps[ [all...] |
H A D | dcn_calcs.c | 404 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;
|
/linux-master/drivers/gpu/drm/amd/display/dc/inc/ |
H A D | dcn_calcs.h | 203 float vtaps[number_of_planes_minus_one + 1]; member in struct:dcn_bw_internal_vars
|
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
H A D | display_mode_vba_30.c | 174 double vtaps, 329 unsigned int vtaps[], 1613 double vtaps, 1624 *VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1); 1626 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); 1911 * dml_max(v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]), 1914 if ((v->htaps[k] > 6 || v->vtaps[k] > 6) 2291 v->vtaps[k], 2776 v->vtaps, 3580 || v->vtaps[ 1610 CalculatePrefetchSourceLines( struct display_mode_lib *mode_lib, double VRatio, double vtaps, bool Interlace, bool ProgressiveToInterlaceUnitInOPP, unsigned int SwathHeight, unsigned int ViewportYStart, double *VInitPreFill, unsigned int *MaxNumSwath) argument 5191 CalculateWatermarksAndDRAMSpeedChangeSupport( struct display_mode_lib *mode_lib, unsigned int PrefetchMode, unsigned int NumberOfActivePlanes, unsigned int MaxLineBufferLines, unsigned int LineBufferSize, unsigned int DPPOutputBufferPixels, unsigned int DETBufferSizeInKByte, unsigned int WritebackInterfaceBufferSize, double DCFCLK, double ReturnBW, bool GPUVMEnable, unsigned int dpte_group_bytes[], unsigned int MetaChunkSize, double UrgentLatency, double ExtraLatency, double WritebackLatency, double WritebackChunkSize, double SOCCLK, double DRAMClockChangeLatency, double SRExitTime, double SREnterPlusExitTime, double DCFCLKDeepSleep, unsigned int DPPPerPlane[], bool DCCEnable[], double DPPCLK[], unsigned int DETBufferSizeY[], unsigned int DETBufferSizeC[], unsigned int SwathHeightY[], unsigned int SwathHeightC[], unsigned int LBBitPerPixel[], double SwathWidthY[], double SwathWidthC[], double HRatio[], double HRatioChroma[], unsigned int vtaps[], unsigned int VTAPsChroma[], double VRatio[], double VRatioChroma[], unsigned int HTotal[], double PixelClock[], unsigned int BlendingAndTiming[], double BytePerPixelDETY[], double BytePerPixelDETC[], double DSTXAfterScaler[], double DSTYAfterScaler[], bool WritebackEnable[], enum source_format_class WritebackPixelFormat[], double WritebackDestinationWidth[], double WritebackDestinationHeight[], double WritebackSourceHeight[], enum clock_change_support *DRAMClockChangeSupport, double *UrgentWatermark, double *WritebackUrgentWatermark, double *DRAMClockChangeWatermark, double *WritebackDRAMClockChangeWatermark, double *StutterExitWatermark, double *StutterEnterPlusExitWatermark, double *MinActiveDRAMClockChangeLatencySupported) argument [all...] |
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | dce_v11_0.c | 740 u32 vtaps; /* vertical scaler taps */ member in struct:dce10_wm_params 943 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 944 (wm->vtaps >= 5) || 1033 if (lb_partitions <= (wm->vtaps + 1)) 1095 wm_high.vtaps = 1; 1097 wm_high.vtaps = 2; 1134 wm_low.vtaps = 1; 1136 wm_low.vtaps = 2;
|
H A D | dce_v10_0.c | 708 u32 vtaps; /* vertical scaler taps */ member in struct:dce10_wm_params 911 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 912 (wm->vtaps >= 5) || 1001 if (lb_partitions <= (wm->vtaps + 1)) 1063 wm_high.vtaps = 1; 1065 wm_high.vtaps = 2; 1102 wm_low.vtaps = 1; 1104 wm_low.vtaps = 2;
|
H A D | dce_v8_0.c | 661 u32 vtaps; /* vertical scaler taps */ member in struct:dce8_wm_params 864 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 865 (wm->vtaps >= 5) || 954 if (lb_partitions <= (wm->vtaps + 1)) 1016 wm_high.vtaps = 1; 1018 wm_high.vtaps = 2; 1055 wm_low.vtaps = 1; 1057 wm_low.vtaps = 2;
|
H A D | dce_v6_0.c | 526 u32 vtaps; /* vertical scaler taps */ member in struct:dce6_wm_params 729 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 730 (wm->vtaps >= 5) || 819 if (lb_partitions <= (wm->vtaps + 1)) 890 wm_high.vtaps = 1; 892 wm_high.vtaps = 2; 917 wm_low.vtaps = 1; 919 wm_low.vtaps = 2;
|
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
H A D | display_mode_vba_31.c | 191 double vtaps, 1738 double vtaps, 1750 *VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1); 1752 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); 1779 dml_print("DML::%s: vtaps = %f\n", __func__, vtaps); 2062 v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]), 2065 if ((v->htaps[k] > 6 || v->vtaps[k] > 6) && v->DPPCLKUsingSingleDPPLuma < 2 * v->PixelClock[k]) { 2422 v->vtaps[k], 3829 || v->VRatio[k] != 1.0 || v->vtaps[ 1735 CalculatePrefetchSourceLines( struct display_mode_lib *mode_lib, double VRatio, double vtaps, bool Interlace, bool ProgressiveToInterlaceUnitInOPP, unsigned int SwathHeight, unsigned int ViewportYStart, double *VInitPreFill, unsigned int *MaxNumSwath) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
H A D | display_mode_vba_314.c | 203 double vtaps, 1758 double vtaps, 1770 *VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1); 1772 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); 1799 dml_print("DML::%s: vtaps = %f\n", __func__, vtaps); 2083 v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]), 2086 if ((v->htaps[k] > 6 || v->vtaps[k] > 6) && v->DPPCLKUsingSingleDPPLuma < 2 * v->PixelClock[k]) { 2444 v->vtaps[k], 3925 || v->VRatio[k] != 1.0 || v->vtaps[ 1755 CalculatePrefetchSourceLines( struct display_mode_lib *mode_lib, double VRatio, double vtaps, bool Interlace, bool ProgressiveToInterlaceUnitInOPP, unsigned int SwathHeight, unsigned int ViewportYStart, double *VInitPreFill, unsigned int *MaxNumSwath) argument [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
H A D | display_mode_vba_32.c | 127 mode_lib->vba.vtaps[k], 447 v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].VTaps = mode_lib->vba.vtaps[k]; 1758 || mode_lib->vba.VRatio[k] != 1.0 || mode_lib->vba.vtaps[k] != 1.0)) { 1760 } else if (mode_lib->vba.vtaps[k] < 1.0 || mode_lib->vba.vtaps[k] > 8.0 || mode_lib->vba.htaps[k] < 1.0 1766 || mode_lib->vba.VRatio[k] > mode_lib->vba.vtaps[k] 1906 mode_lib->vba.htaps[k], mode_lib->vba.HTAPsChroma[k], mode_lib->vba.vtaps[k], 1940 / (mode_lib->vba.vtaps[k] + dml_max(dml_ceil(mode_lib->vba.VRatio[k], 1.0) - 2, 0.0)); 2741 v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].VTaps = mode_lib->vba.vtaps[k];
|
H A D | display_mode_vba_util_32.c | 4406 LBLatencyHidingSourceLinesY[k] = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSizeFinal / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1); 4415 dml_print("DML::%s: k=%d, v->vtaps = %d\n", __func__, k, v->vtaps[k]);
|
/linux-master/drivers/gpu/drm/radeon/ |
H A D | si.c | 2046 u32 vtaps; /* vertical scaler taps */ member in struct:dce6_wm_params 2201 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 2202 (wm->vtaps >= 5) || 2260 if (lb_partitions <= (wm->vtaps + 1)) 2323 wm_high.vtaps = 1; 2325 wm_high.vtaps = 2; 2350 wm_low.vtaps = 1; 2352 wm_low.vtaps = 2;
|
H A D | evergreen.c | 1947 u32 vtaps; /* vertical scaler taps */ member in struct:evergreen_wm_params 2084 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 2085 (wm->vtaps >= 5) || 2141 if (lb_partitions <= (wm->vtaps + 1)) 2201 wm_high.vtaps = 1; 2203 wm_high.vtaps = 2; 2228 wm_low.vtaps = 1; 2230 wm_low.vtaps = 2;
|
H A D | cik.c | 8911 u32 vtaps; /* vertical scaler taps */ member in struct:dce8_wm_params 9114 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 9115 (wm->vtaps >= 5) || 9204 if (lb_partitions <= (wm->vtaps + 1)) 9267 wm_high.vtaps = 1; 9269 wm_high.vtaps = 2; 9307 wm_low.vtaps = 1; 9309 wm_low.vtaps = 2;
|