Searched refs:vready_after_vcount0 (Results 1 - 15 of 15) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_rq_dlg_calc_32.c235 unsigned int vready_after_vcount0; local
288 vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes,
290 dlg_regs->vready_after_vcount0 = vready_after_vcount0;
292 dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, dlg_regs->vready_after_vcount0);
/linux-master/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml_display_rq_dlg_calc.c220 dml_uint_t vready_after_vcount0; local
329 vready_after_vcount0 = (dml_uint_t)(dml_get_vready_at_or_after_vsync(mode_lib, pipe_idx));
330 disp_dlg_regs->vready_after_vcount0 = vready_after_vcount0;
332 dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, disp_dlg_regs->vready_after_vcount0);
H A Ddisplay_mode_util.c294 dml_print("DML: vready_after_vcount0 = 0x%x\n", dlg_regs->vready_after_vcount0);
H A Ddml2_translation_helper.c1259 out->dlg_regs.vready_after_vcount0 = disp_dlg_regs->vready_after_vcount0;
H A Ddisplay_mode_core_structs.h1913 dml_uint_t vready_after_vcount0; member in struct:_vcs_dpi_dml_display_dlg_regs_st
/linux-master/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_rq_dlg_helpers.c307 "DML_RQ_DLG_CALC: vready_after_vcount0 = 0x%0x\n",
308 dlg_regs->vready_after_vcount0);
H A Ddisplay_mode_structs.h657 unsigned int vready_after_vcount0; member in struct:_vcs_dpi_display_dlg_regs_st
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.c1081 disp_dlg_regs->vready_after_vcount0 = 1;
1083 disp_dlg_regs->vready_after_vcount0 = 0;
1088 disp_dlg_regs->vready_after_vcount0 = 1;
1090 disp_dlg_regs->vready_after_vcount0 = 0;
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20v2.c1042 disp_dlg_regs->vready_after_vcount0 = 1;
1044 disp_dlg_regs->vready_after_vcount0 = 0;
1049 disp_dlg_regs->vready_after_vcount0 = 1;
1051 disp_dlg_regs->vready_after_vcount0 = 0;
H A Ddisplay_rq_dlg_calc_20.c1041 disp_dlg_regs->vready_after_vcount0 = 1;
1043 disp_dlg_regs->vready_after_vcount0 = 0;
1048 disp_dlg_regs->vready_after_vcount0 = 1;
1050 disp_dlg_regs->vready_after_vcount0 = 0;
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_rq_dlg_calc_31.c1036 disp_dlg_regs->vready_after_vcount0 = 1;
1038 disp_dlg_regs->vready_after_vcount0 = 0;
1041 disp_dlg_regs->vready_after_vcount0 = 1;
1043 disp_dlg_regs->vready_after_vcount0 = 0;
1046 dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, disp_dlg_regs->vready_after_vcount0);
1048 //old_impl_vs_vba_impl("vready_after_vcount0", disp_dlg_regs->vready_after_vcount0, vba__vready_after_vcount0);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_rq_dlg_calc_314.c1123 disp_dlg_regs->vready_after_vcount0 = 1;
1125 disp_dlg_regs->vready_after_vcount0 = 0;
1128 disp_dlg_regs->vready_after_vcount0 = 1;
1130 disp_dlg_regs->vready_after_vcount0 = 0;
1133 dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, disp_dlg_regs->vready_after_vcount0);
1135 //old_impl_vs_vba_impl("vready_after_vcount0", disp_dlg_regs->vready_after_vcount0, vba__vready_after_vcount0);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_rq_dlg_calc_30.c1139 disp_dlg_regs->vready_after_vcount0 = 1;
1141 disp_dlg_regs->vready_after_vcount0 = 0;
1146 disp_dlg_regs->vready_after_vcount0 = 1;
1148 disp_dlg_regs->vready_after_vcount0 = 0;
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer_debug.c276 dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c260 dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,

Completed in 216 milliseconds