Searched refs:vmcr (Results 1 - 10 of 10) sorted by relevance

/linux-master/arch/arm64/kvm/
H A Dvgic-sys-reg-v3.c18 struct vgic_vmcr vmcr; local
20 vgic_get_vmcr(vcpu, &vmcr);
52 vmcr.cbpr = FIELD_GET(ICC_CTLR_EL1_CBPR_MASK, val);
53 vmcr.eoim = FIELD_GET(ICC_CTLR_EL1_EOImode_MASK, val);
54 vgic_set_vmcr(vcpu, &vmcr);
63 struct vgic_vmcr vmcr; local
66 vgic_get_vmcr(vcpu, &vmcr);
79 val |= FIELD_PREP(ICC_CTLR_EL1_CBPR_MASK, vmcr.cbpr);
80 val |= FIELD_PREP(ICC_CTLR_EL1_EOImode_MASK, vmcr.eoim);
90 struct vgic_vmcr vmcr; local
102 struct vgic_vmcr vmcr; local
113 struct vgic_vmcr vmcr; local
125 struct vgic_vmcr vmcr; local
136 struct vgic_vmcr vmcr; local
150 struct vgic_vmcr vmcr; local
165 struct vgic_vmcr vmcr; local
177 struct vgic_vmcr vmcr; local
188 struct vgic_vmcr vmcr; local
200 struct vgic_vmcr vmcr; local
[all...]
/linux-master/arch/arm64/kvm/hyp/
H A Dvgic-v3-sr.c463 void __vgic_v3_write_vmcr(u32 vmcr) argument
465 write_gicreg(vmcr, ICH_VMCR_EL2);
484 static int __vgic_v3_highest_priority_lr(struct kvm_vcpu *vcpu, u32 vmcr, argument
500 if (!(val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG0_MASK))
504 if ((val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG1_MASK))
575 static unsigned int __vgic_v3_get_bpr0(u32 vmcr) argument
577 return (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
580 static unsigned int __vgic_v3_get_bpr1(u32 vmcr) argument
584 if (vmcr & ICH_VMCR_CBPR_MASK) {
585 bpr = __vgic_v3_get_bpr0(vmcr);
599 __vgic_v3_pri_to_pre(u8 pri, u32 vmcr, int grp) argument
617 __vgic_v3_set_active_priority(u8 pri, u32 vmcr, int grp) argument
674 __vgic_v3_read_iar(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
730 __vgic_v3_write_dir(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
753 __vgic_v3_write_eoir(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
788 __vgic_v3_read_igrpen0(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
793 __vgic_v3_read_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
798 __vgic_v3_write_igrpen0(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
810 __vgic_v3_write_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
822 __vgic_v3_read_bpr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
827 __vgic_v3_read_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
832 __vgic_v3_write_bpr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
849 __vgic_v3_write_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
891 __vgic_v3_read_apxr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
897 __vgic_v3_read_apxr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
903 __vgic_v3_read_apxr2(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
908 __vgic_v3_read_apxr3(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
913 __vgic_v3_write_apxr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
918 __vgic_v3_write_apxr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
923 __vgic_v3_write_apxr2(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
928 __vgic_v3_write_apxr3(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
933 __vgic_v3_read_hppir(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
952 __vgic_v3_read_pmr(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
959 __vgic_v3_write_pmr(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
971 __vgic_v3_read_rpr(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
977 __vgic_v3_read_ctlr(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
999 __vgic_v3_write_ctlr(struct kvm_vcpu *vcpu, u32 vmcr, int rt) argument
1020 u32 vmcr; local
[all...]
/linux-master/arch/arm64/kvm/vgic/
H A Dvgic-mmio-v2.c278 struct vgic_vmcr vmcr; local
281 vgic_get_vmcr(vcpu, &vmcr);
285 val = vmcr.grpen0 << GIC_CPU_CTRL_EnableGrp0_SHIFT;
286 val |= vmcr.grpen1 << GIC_CPU_CTRL_EnableGrp1_SHIFT;
287 val |= vmcr.ackctl << GIC_CPU_CTRL_AckCtl_SHIFT;
288 val |= vmcr.fiqen << GIC_CPU_CTRL_FIQEn_SHIFT;
289 val |= vmcr.cbpr << GIC_CPU_CTRL_CBPR_SHIFT;
290 val |= vmcr.eoim << GIC_CPU_CTRL_EOImodeNS_SHIFT;
301 val = (vmcr.pmr & GICV_PMR_PRIORITY_MASK) >>
305 val = vmcr
326 struct vgic_vmcr vmcr; local
[all...]
H A Dvgic-v2.c208 u32 vmcr; local
210 vmcr = (vmcrp->grpen0 << GICH_VMCR_ENABLE_GRP0_SHIFT) &
212 vmcr |= (vmcrp->grpen1 << GICH_VMCR_ENABLE_GRP1_SHIFT) &
214 vmcr |= (vmcrp->ackctl << GICH_VMCR_ACK_CTL_SHIFT) &
216 vmcr |= (vmcrp->fiqen << GICH_VMCR_FIQ_EN_SHIFT) &
218 vmcr |= (vmcrp->cbpr << GICH_VMCR_CBPR_SHIFT) &
220 vmcr |= (vmcrp->eoim << GICH_VMCR_EOI_MODE_SHIFT) &
222 vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
224 vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
226 vmcr |
235 u32 vmcr; local
[all...]
H A Dvgic-v3.c198 u32 vmcr; local
201 vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) &
203 vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) &
210 vmcr = ICH_VMCR_FIQ_EN_MASK;
213 vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
214 vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
215 vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
216 vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
217 vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
218 vmcr |
228 u32 vmcr; local
[all...]
H A Dvgic.h206 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
207 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
242 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
243 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
274 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
275 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
H A Dvgic-mmio.c843 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) argument
846 vgic_v2_set_vmcr(vcpu, vmcr);
848 vgic_v3_set_vmcr(vcpu, vmcr);
851 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr) argument
854 vgic_v2_get_vmcr(vcpu, vmcr);
856 vgic_v3_get_vmcr(vcpu, vmcr);
H A Dvgic.c959 struct vgic_vmcr vmcr; local
967 vgic_get_vmcr(vcpu, &vmcr);
975 irq->priority < vmcr.pmr;
/linux-master/arch/arm64/include/asm/
H A Dkvm_asm.h245 extern void __vgic_v3_write_vmcr(u32 vmcr);
/linux-master/drivers/video/fbdev/
H A Dcg14.c125 u32 vmcr; /* VBC Master Control */ member in struct:cg14_regs

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