Searched refs:timeline (Results 1 - 25 of 47) sorted by relevance

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/linux-master/drivers/gpu/drm/i915/gt/selftests/
H A Dmock_timeline.c11 void mock_timeline_init(struct intel_timeline *timeline, u64 context) argument
13 timeline->gt = NULL;
14 timeline->fence_context = context;
16 mutex_init(&timeline->mutex);
18 INIT_ACTIVE_FENCE(&timeline->last_request);
19 INIT_LIST_HEAD(&timeline->requests);
21 i915_syncmap_init(&timeline->sync);
23 INIT_LIST_HEAD(&timeline->link);
26 void mock_timeline_fini(struct intel_timeline *timeline) argument
28 i915_syncmap_free(&timeline
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H A Dmock_timeline.h14 void mock_timeline_init(struct intel_timeline *timeline, u64 context);
15 void mock_timeline_fini(struct intel_timeline *timeline);
/linux-master/tools/testing/selftests/sync/
H A Dsync_alloc.c34 int timeline, valid; local
36 timeline = sw_sync_timeline_create();
37 valid = sw_sync_timeline_is_valid(timeline);
38 ASSERT(valid, "Failure allocating timeline\n");
40 sw_sync_timeline_destroy(timeline);
46 int timeline, fence, valid; local
48 timeline = sw_sync_timeline_create();
49 valid = sw_sync_timeline_is_valid(timeline);
50 ASSERT(valid, "Failure allocating timeline\n");
52 fence = sw_sync_fence_create(timeline, "allocFenc
63 int fence, timeline; local
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H A Dsync_fence.c2 * sync fence tests with one timeline
35 int timeline = sw_sync_timeline_create(); local
37 valid = sw_sync_timeline_is_valid(timeline);
38 ASSERT(valid, "Failure allocating timeline\n");
40 fence = sw_sync_fence_create(timeline, "allocFence", 5);
48 /* Advance timeline from 0 -> 1 */
49 ret = sw_sync_timeline_inc(timeline, 1);
50 ASSERT(ret == 0, "Failure advancing timeline\n");
57 ret = sw_sync_timeline_inc(timeline, 4);
65 ret = sw_sync_timeline_inc(timeline, 1
79 int timeline = sw_sync_timeline_create(); local
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H A Dsync_merge.c35 int timeline = sw_sync_timeline_create(); local
37 valid = sw_sync_timeline_is_valid(timeline);
38 ASSERT(valid, "Failure allocating timeline\n");
40 fence = sw_sync_fence_create(timeline, "allocFence", 5);
51 sw_sync_timeline_inc(timeline, 5);
57 sw_sync_timeline_destroy(timeline);
H A Dsync_stress_parallelism.c36 int timeline; member in struct:__anon15382
43 int timeline = test_data_two_threads.timeline; local
48 fence = sw_sync_fence_create(timeline, "fence",
66 ret = sw_sync_timeline_inc(timeline, 1);
67 ASSERT(ret == 0, "Advancing timeline failed\n");
79 int timeline = sw_sync_timeline_create(); local
81 valid = sw_sync_timeline_is_valid(timeline);
82 ASSERT(valid, "Failure allocating timeline\n");
86 test_data_two_threads.timeline
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H A Dsync_stress_merge.c44 int timeline, timeline_offset, sync_point; local
65 timeline = timelines[timeline_offset];
68 /* Keep track of the latest sync_point in each timeline. */
75 tmpfence = sw_sync_fence_create(timeline, "fence", sync_point);
100 /* Increment the timeline to the last sync_point */
/linux-master/drivers/dma-buf/
H A Dsync_trace.h13 TP_PROTO(struct sync_timeline *timeline),
15 TP_ARGS(timeline),
18 __string(name, timeline->name)
23 __assign_str(name, timeline->name);
24 __entry->value = timeline->value;
/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_timeline.c58 intel_timeline_pin_map(struct intel_timeline *timeline) argument
60 struct drm_i915_gem_object *obj = timeline->hwsp_ggtt->obj;
61 u32 ofs = offset_in_page(timeline->hwsp_offset);
68 timeline->hwsp_map = vaddr;
69 timeline->hwsp_seqno = memset(vaddr + ofs, 0, TIMELINE_SEQNO_BYTES);
75 static int intel_timeline_init(struct intel_timeline *timeline, argument
80 kref_init(&timeline->kref);
81 atomic_set(&timeline->pin_count, 0);
83 timeline->gt = gt;
86 timeline
125 struct intel_timeline *timeline = local
150 struct intel_timeline *timeline; local
393 struct intel_timeline *timeline = local
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H A Dintel_timeline.h33 intel_timeline_get(struct intel_timeline *timeline) argument
35 kref_get(&timeline->kref);
36 return timeline;
40 static inline void intel_timeline_put(struct intel_timeline *timeline) argument
42 kref_put(&timeline->kref, __intel_timeline_free);
H A Dintel_engine_pm.c84 ce->timeline->seqno,
85 READ_ONCE(*ce->timeline->hwsp_seqno),
87 GEM_BUG_ON(ce->timeline->seqno !=
88 READ_ONCE(*ce->timeline->hwsp_seqno));
130 * engine->wakeref.counter or our timeline->active_count.
145 /* Let new submissions commence (and maybe retire this timeline) */
175 GEM_BUG_ON(ce->timeline->hwsp_ggtt != engine->status_page.vma);
182 * Note, we do this without taking the timeline->mutex. We cannot
184 * already underneath the timeline->mutex. Instead we rely on the
188 * the context, as they assume protection by the timeline
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H A Dintel_engine_heartbeat.c213 if (!mutex_trylock(&ce->timeline->mutex)) {
214 /* Unable to lock the kernel timeline, is the engine stuck? */
230 mutex_unlock(&ce->timeline->mutex);
281 lockdep_assert_held(&ce->timeline->mutex);
336 err = mutex_lock_interruptible(&ce->timeline->mutex);
351 mutex_unlock(&ce->timeline->mutex);
370 if (!mutex_lock_interruptible(&ce->timeline->mutex)) {
372 mutex_unlock(&ce->timeline->mutex);
393 if (mutex_lock_interruptible(&ce->timeline->mutex)) {
408 mutex_unlock(&ce->timeline
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H A Dintel_context.c187 err = intel_timeline_pin(ce->timeline, ww);
202 intel_timeline_unpin(ce->timeline);
213 intel_timeline_unpin(ce->timeline);
231 * We always pin the context/ring/timeline here, to ensure a pin
236 err = i915_gem_object_lock(ce->timeline->hwsp_ggtt->obj, ww);
305 i915_gem_ww_unlock_single(ce->timeline->hwsp_ggtt->obj);
371 __intel_timeline_pin(ce->timeline);
440 if (ce->timeline)
441 intel_timeline_put(ce->timeline);
471 intel_timeline_enter(ce->timeline);
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H A Dintel_context.h25 ce__->timeline->fence_context, \
210 lockdep_assert_held(&ce->timeline->mutex);
220 lockdep_assert(lockdep_is_held(&ce->timeline->mutex) ||
227 lockdep_assert_held(&ce->timeline->mutex);
249 __acquires(&ce->timeline->mutex)
251 struct intel_timeline *tl = ce->timeline;
H A Dmock_engine.c156 mock_timeline_unpin(ce->timeline);
171 ce->timeline = intel_timeline_create(ce->engine->gt);
172 if (IS_ERR(ce->timeline)) {
174 return PTR_ERR(ce->timeline);
177 err = mock_timeline_pin(ce->timeline);
179 intel_timeline_put(ce->timeline);
180 ce->timeline = NULL;
267 * Virtual engines complicate acquiring the engine timeline lock,
417 engine->status_page.vma = ce->timeline->hwsp_ggtt;
H A Dintel_ring_submission.c576 ce->timeline = intel_timeline_get(engine->legacy.timeline);
1070 intel_timeline_unpin(engine->legacy.timeline);
1071 intel_timeline_put(engine->legacy.timeline);
1143 * Using a global execution timeline; the previous final breadcrumb is
1316 struct intel_timeline *timeline; local
1341 timeline = intel_timeline_create_from_engine(engine,
1343 if (IS_ERR(timeline)) {
1344 err = PTR_ERR(timeline);
1347 GEM_BUG_ON(timeline
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H A Dselftest_timeline.c520 pr_err("Failed to write to timeline!\n");
585 GEM_TRACE_ERR("Invalid seqno:%lu stored in timeline %llu @ %x, found 0x%x\n",
657 GEM_TRACE_ERR("Invalid seqno:%lu stored in timeline %llu @ %x, found 0x%x\n",
751 pr_err("Wait for timeline writes timed out!\n");
758 pr_err("Bad timeline values: found (%x, %x), expected (%x, %x)\n",
838 /* keep the same cache settings as timeline */
863 lockdep_unpin_lock(&from->context->timeline->mutex, from->cookie);
864 mutex_unlock(&from->context->timeline->mutex);
868 mutex_lock(&to->context->timeline->mutex);
869 to->cookie = lockdep_pin_lock(&to->context->timeline
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H A Dintel_context_types.h115 struct intel_timeline *timeline; member in struct:intel_context
162 unsigned int active_count; /* protected by timeline->mutex */
/linux-master/drivers/gpu/drm/i915/gem/
H A Di915_gem_throttle.c66 if (!ce->timeline)
69 mutex_lock(&ce->timeline->mutex);
71 &ce->timeline->requests,
83 mutex_unlock(&ce->timeline->mutex);
/linux-master/include/trace/events/
H A Ddma_fence.h20 __string(timeline, fence->ops->get_timeline_name(fence))
27 __assign_str(timeline, fence->ops->get_timeline_name(fence));
32 TP_printk("driver=%s timeline=%s context=%u seqno=%u",
33 __get_str(driver), __get_str(timeline), __entry->context,
/linux-master/drivers/gpu/drm/i915/
H A Di915_active.c30 u64 timeline; member in struct:active_node
156 /* Make the cached node available for reuse with any timeline */
157 ref->cache->timeline = 0; /* needs cmpxchg(u64) */
169 /* Finally free the discarded timeline tree */
236 GEM_BUG_ON(idx == 0); /* 0 is the unordered timeline, rsvd for cache */
239 * We track the most recently used timeline to skip a rbtree search
243 * current timeline.
247 u64 cached = READ_ONCE(it->timeline);
254 * An unclaimed cache [.timeline=0] can only be claimed once.
258 * idx. If, and only if, the timeline i
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H A Di915_request.h214 struct intel_timeline __rcu *timeline; member in struct:i915_request
228 * We pin the timeline->mutex while constructing the request to
230 * The timeline->mutex must be held to ensure that only this caller
231 * can use the ring and manipulate the associated timeline during
275 * the HW status page (or our timeline's local equivalent). The full
276 * path would be rq->hw_context->ring->timeline->hwsp_seqno.
320 /* timeline->request entry for this request */
500 * the local timeline's equivalent) for this request. The request itself
524 * If the timeline is not using initial breadcrumbs, a request is
525 * considered started if the previous request on its timeline (
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H A Di915_request.c70 * The timeline struct (as part of the ppgtt underneath a context)
742 * to the engine timeline (__i915_request_submit()). The waiters
896 struct intel_timeline *tl = ce->timeline;
958 RCU_INIT_POINTER(rq->timeline, tl);
1064 if (i915_request_timeline(rq) == rcu_access_pointer(signal->timeline))
1088 /* Is signal the earliest request on its timeline? */
1089 if (pos == &rcu_dereference(signal->timeline)->requests)
1093 * Peek at the request before us in the timeline. That
1096 * still part of the signaler's timeline.
1171 * the timeline HWS
1635 __i915_request_ensure_parallel_ordering(struct i915_request *rq, struct intel_timeline *timeline) argument
1670 __i915_request_ensure_ordering(struct i915_request *rq, struct intel_timeline *timeline) argument
1721 struct intel_timeline *timeline = i915_request_timeline(rq); local
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H A Di915_scheduler.c139 * Virtual engines complicate acquiring the engine timeline lock,
249 /* Recheck after acquiring the engine->timeline.lock */
383 * However, retirement is run independently on each timeline and
425 /* Dependencies along the same timeline are expected. */
426 if (signaler->timeline == rq->timeline)
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_trace.h171 __string(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job))
181 __assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job));
187 TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u",
188 __entry->sched_job_id, __get_str(timeline), __entry->context,
197 __string(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job))
206 __assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job));
212 TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u",
213 __entry->sched_job_id, __get_str(timeline), __entry->context,

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