Searched refs:tiles (Results 1 - 25 of 28) sorted by relevance

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/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dnv25.c33 u32 tiles = DIV_ROUND_UP(size, 0x40); local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40);
H A Dnv40.c33 u32 tiles = DIV_ROUND_UP(size, 0x80); local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x100);
H A Dnv36.c33 u32 tiles = DIV_ROUND_UP(size, 0x40); local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40);
H A Dnv35.c33 u32 tiles = DIV_ROUND_UP(size, 0x40); local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40);
H A Dnv20.c46 u32 tiles = DIV_ROUND_UP(size, 0x40); local
47 u32 tags = round_up(tiles / fb->ram->parts, 0x40);
H A Dnv30.c52 u32 tiles = DIV_ROUND_UP(size, 0x40); local
53 u32 tags = round_up(tiles / fb->ram->parts, 0x40);
/linux-master/drivers/gpu/drm/xe/
H A Dxe_device.h54 return &xe->tiles[0];
85 gt = xe->tiles[gt_id].primary_gt;
121 for_each_if((tile__) = &(xe__)->tiles[(id__)])
125 for_each_if((tile__) = &(xe__)->tiles[(id__)])
H A Dxe_gsc_proxy.c348 struct xe_gt *gt = xe->tiles[0].media_gt;
363 struct xe_gt *gt = xe->tiles[0].media_gt;
H A Dxe_device_types.h115 * at the root tile, and the MSTR_TILE_INTR register will report which tiles
172 * still be accessed by all tiles' GTs.
247 /** @info.tile_count: Number of tiles */
375 /** @tiles: device tiles */
376 struct xe_tile tiles[XE_MAX_TILES_PER_DEVICE]; member in struct:xe_device
H A Dxe_ttm_vram_mgr.c378 struct xe_tile *tile = &xe->tiles[res->mem_type - XE_PL_VRAM0];
H A Dxe_query.c542 struct xe_guc *guc = &xe->tiles[0].primary_gt->uc.guc;
H A Dxe_hwmon.c765 hwmon->gt = xe->tiles[0].primary_gt;
H A Dxe_bo.c123 tile = &xe->tiles[mem_type == XE_PL_STOLEN ? 0 : (mem_type - XE_PL_VRAM0)];
714 migrate = xe->tiles[0].migrate;
/linux-master/arch/arm/include/debug/
H A Dvexpress.S28 @ - all other (RS1 complaint) tiles use UART mapped
/linux-master/drivers/pinctrl/qcom/
H A Dpinctrl-msm.h160 const char *const *tiles; member in struct:msm_pinctrl_soc_data
H A Dpinctrl-msm.c58 * @regs: Base addresses for the TLMM tiles.
1548 if (soc_data->tiles) {
1551 soc_data->tiles[i]);
H A Dpinctrl-sc8180x.c27 * used to locate different tiles for ACPI probe.
1592 .tiles = sc8180x_tiles,
1606 .tiles = sc8180x_tiles,
1618 * hardware layout of 3 separate tiles. Let's split the memory resource into
1630 * DT already has tiles defined properly, so nothing needs to be done
H A Dpinctrl-sm6115.c888 .tiles = sm6115_tiles,
H A Dpinctrl-sdm660.c1422 .tiles = sdm660_tiles,
H A Dpinctrl-sc7180.c1138 .tiles = sc7180_tiles,
H A Dpinctrl-sm6125.c1247 .tiles = sm6125_tiles,
H A Dpinctrl-sm7150.c1233 .tiles = sm7150_tiles,
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_fb.c49 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
929 unsigned int tiles; local
935 tiles = (old_offset - new_offset) / tile_size;
937 *y += tiles / pitch_tiles * tile_height;
938 *x += tiles % pitch_tiles * tile_width;
1040 unsigned int tile_rows, tiles, pitch_tiles; local
1055 tiles = *x / tile_width;
1058 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
1368 * of 8 main surface tiles.
1561 /* Return number of tiles
1567 unsigned int tiles; local
[all...]
/linux-master/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_vp9_req_lat_if.c275 struct vdec_vp9_slice_tiles tiles; member in struct:vdec_vp9_slice_frame
887 struct vdec_vp9_slice_tiles *tiles; local
897 tiles = &vsi->frame.tiles;
898 tiles->actual_rows = 0;
911 tiles->mi_rows[i] = (offset + 7) >> 3;
912 if (tiles->mi_rows[i])
913 tiles->actual_rows++;
920 tiles->mi_cols[i] = (offset + 7) >> 3;
1058 * parse tiles accordin
1079 struct vdec_vp9_slice_tiles *tiles; local
[all...]
/linux-master/drivers/media/platform/verisilicon/
H A Dhantro_g2_vp9_dec.c238 static void recompute_tile_info(unsigned short *tile_info, unsigned int tiles, unsigned int sbs) argument
244 for (i = 1; i <= tiles; ++i) {
245 next_accumulated = i * sbs / tiles;
353 /* provide aux buffers even if no tiles are used */

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