Searched refs:stores (Results 1 - 25 of 26) sorted by relevance

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/linux-master/arch/sparc/kernel/
H A Ddtlb_prot.S12 * [TL == 0] 1) User stores to readonly pages.
13 * [TL == 0] 2) Nucleus stores to user readonly pages.
14 * [TL > 0] 3) Nucleus stores to user readonly stack frame.
20 membar #Sync ! Synchronize stores
/linux-master/arch/mips/include/asm/
H A Dmips-r2-to-r6-emul.h23 u64 stores; member in struct:mips_r2_emulator_stats
H A Dfpu_emulator.h27 unsigned long stores; member in struct:mips_fpu_emulator_stats
/linux-master/fs/xfs/scrub/
H A Dxfarray.h139 uint64_t stores; member in struct:xfarray_sortinfo
H A Dtrace.h1115 __field(unsigned long long, stores)
1127 __entry->stores = si->stores;
1137 "xfino 0x%lx loads %llu stores %llu compares %llu heapsorts %llu stack_depth %u/%u error %d",
1144 __entry->stores,
H A Dxfarray.c375 # define xfarray_sort_bump_stores(si) do { (si)->stores++; } while (0)
/linux-master/tools/testing/selftests/kvm/x86_64/
H A Dpmu_event_filter_test.c60 uint64_t stores; member in struct:__anon992
453 const uint64_t stores = rdmsr(msr_base + 1); local
464 pmc_results.stores = rdmsr(msr_base + 1) - stores;
536 * For each test, the guest enables 3 PMU counters (loads, stores,
537 * loads + stores). The filter is then set in KVM with the masked events
558 .msg = "Only allow stores.",
567 .msg = "Only allow loads + stores.",
577 .msg = "Only allow loads and stores.",
588 .msg = "Only allow loads and loads + stores
[all...]
/linux-master/arch/sparc/lib/
H A DM7memset.S32 * For small 6 or fewer bytes stores, bytes will be stored.
34 * For less than 32 bytes stores, align the address on 4 byte boundary.
41 * Using BIS stores, set the first long word of each
46 * Using BIS stores, set the first long word of each of
66 * similar to prefetching for normal stores.
71 * BIS stores must be followed by a membar #StoreStore. The benefit of
79 * store and the final stores.
167 ! Use long word stores.
179 and %o2, 63, %o3 ! %o3 = bytes left after blk stores.
187 ! initial cache-clearing stores
[all...]
H A DM7memcpy.S128 * between the first initializing store and the final stores.
434 ! lines from memory. Use ST_CHUNK stores to first element of each cache
437 ! Initial stores using MRU version of BIS to keep cache line in
444 ! We use STORE_MRU_ASI for the first seven stores to each cache line
452 ! the store miss buffer. Then the matching stores for all those
/linux-master/arch/powerpc/lib/
H A Dmemcpy_64.S115 ld r9,0(r4) # 3+2n loads, 2+2n stores
127 0: ld r0,0(r4) # 4+2n loads, 3+2n stores
/linux-master/tools/testing/selftests/powerpc/copyloops/
H A Dmemcpy_64.S115 ld r9,0(r4) # 3+2n loads, 2+2n stores
127 0: ld r0,0(r4) # 4+2n loads, 3+2n stores
/linux-master/arch/mips/math-emu/
H A Dme-debugfs.c56 __this_cpu_write((fpuemustats).stores, 0);
212 FPU_STAT_CREATE(stores);
H A Dcp1emu.c1070 MIPS_FPU_EMU_INC_STATS(stores);
1104 MIPS_FPU_EMU_INC_STATS(stores);
1501 MIPS_FPU_EMU_INC_STATS(stores);
1610 MIPS_FPU_EMU_INC_STATS(stores);
/linux-master/arch/mips/kernel/
H A Dmips-r2-to-r6-emul.c1418 MIPS_R2_STATS(stores);
1488 MIPS_R2_STATS(stores);
1845 MIPS_R2_STATS(stores);
1963 MIPS_R2_STATS(stores);
2269 seq_printf(s, "stores\t\t%ld\t%ld\n",
2270 (unsigned long)__this_cpu_read(mipsr2emustats.stores),
2271 (unsigned long)__this_cpu_read(mipsr2bdemustats.stores));
2326 __this_cpu_write((mipsr2emustats).stores, 0);
2327 __this_cpu_write((mipsr2bdemustats).stores, 0);
/linux-master/arch/arm/crypto/
H A Daes-ce-core.S328 vst1.8 {q2}, [r4] @ overlapping stores
366 vst1.8 {q1}, [r4] @ overlapping stores
584 vst1.8 {q2}, [r4] @ overlapping stores
676 vst1.8 {q2}, [r4] @ overlapping stores
/linux-master/arch/alpha/lib/
H A Dev6-copy_user.S64 EXI( ldbu $1,0($17) ) # .. .. .. L : Keep loads separate from stores
/linux-master/arch/powerpc/perf/
H A Dpower10-pmu.c128 GENERIC_EVENT_ATTR(mem-stores, MEM_STORES);
144 CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST);
H A Dpower9-pmu.c175 GENERIC_EVENT_ATTR(mem-stores, MEM_STORES);
H A Dpower8-pmu.c146 CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST);
/linux-master/arch/m68k/fpsp040/
H A Dx_operr.S243 | This routine stores the data in d0, for the given size in d1,
/linux-master/tools/perf/util/
H A Dparse-events.l172 lc_op_result (load|loads|read|store|stores|write|prefetch|prefetches|speculative-read|speculative-load|refs|Reference|ops|access|misses|miss)
/linux-master/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler_gfx9.asm47 var ACK_SQC_STORE = 1 //workaround for suspected SQC store bug causing incorrect stores under concurrency
971 // If STATUS.ALLOW_REPLAY=0 and TRAPSTS.XNACK_ERROR=1 then TCP stores will fail.
H A Dcwsr_trap_handler_gfx10.asm1312 // If TRAPSTS.XNACK_ERROR=1 then TCP stores will fail.
/linux-master/arch/x86/events/intel/
H A Dcore.c375 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
2126 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6");
5394 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
5482 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2");
5785 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small);
/linux-master/arch/x86/crypto/
H A Daesni-intel_asm.S561 # Reads DLEN bytes starting at DPTR and stores in XMMDst

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