/linux-master/drivers/net/ethernet/microchip/sparx5/ |
H A D | sparx5_vlan.c | 18 spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid)); 19 spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); 20 spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid)); 143 spx5_wr(0, spx5, ANA_AC_PGID_CFG(pgid)); 144 spx5_wr(0, spx5, ANA_AC_PGID_CFG1(pgid)); 145 spx5_wr(0, spx5, ANA_AC_PGID_CFG2(pgid)); 166 spx5_wr(mask[0], sparx5, ANA_AC_PGID_CFG(port)); 167 spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port)); 168 spx5_wr(mask[2], sparx5, ANA_AC_PGID_CFG2(port)); 178 spx5_wr(mas [all...] |
H A D | sparx5_psfp.c | 105 spx5_wr(ANA_AC_SG_ACCESS_CTRL_SGID_SET(id), sparx5, 108 spx5_wr(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(1) | 143 spx5_wr(ANA_AC_SG_ACCESS_CTRL_SGID_SET(id), sparx5, 147 spx5_wr(sg->basetime.tv_nsec, sparx5, ANA_AC_SG_CONFIG_REG_1); 148 spx5_wr(base_lsb, sparx5, ANA_AC_SG_CONFIG_REG_2); 162 spx5_wr(sg->cycletime, sparx5, ANA_AC_SG_CONFIG_REG_4); 163 spx5_wr(sg->cycletimeext, sparx5, ANA_AC_SG_CONFIG_REG_5); 172 spx5_wr(ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(ips) | 177 spx5_wr(accum_time_interval, sparx5, 181 spx5_wr(gc [all...] |
H A D | sparx5_packet.c | 26 spx5_wr(QS_XTR_FLUSH_FLUSH_SET(BIT(grp)), sparx5, QS_XTR_FLUSH); 32 spx5_wr(0, sparx5, QS_XTR_FLUSH); 179 spx5_wr(QS_INJ_CTRL_SOF_SET(1) | 185 spx5_wr(ifh[w], sparx5, QS_INJ_WR(grp)); 192 spx5_wr(val, sparx5, QS_INJ_WR(grp)); 197 spx5_wr(0, sparx5, QS_INJ_WR(grp)); 202 spx5_wr(QS_INJ_CTRL_GAP_SIZE_SET(1) | 208 spx5_wr(0, sparx5, QS_INJ_WR(grp)); 307 spx5_wr(QS_XTR_GRP_CFG_MODE_SET(1) | 311 spx5_wr(QS_INJ_GRP_CFG_MODE_SE [all...] |
H A D | sparx5_fdma.c | 116 spx5_wr(((u64)rx->dma) & GENMASK(31, 0), sparx5, 118 spx5_wr(((u64)rx->dma) >> 32, sparx5, FDMA_DCB_LLP1(rx->channel_id)); 121 spx5_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(FDMA_RX_DCB_MAX_DBS) | 141 spx5_wr(BIT(rx->channel_id), sparx5, FDMA_CH_ACTIVATE); 162 spx5_wr(((u64)tx->dma) & GENMASK(31, 0), sparx5, 164 spx5_wr(((u64)tx->dma) >> 32, sparx5, FDMA_DCB_LLP1(tx->channel_id)); 167 spx5_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(FDMA_TX_DCB_MAX_DBS) | 177 spx5_wr(BIT(tx->channel_id), sparx5, FDMA_CH_ACTIVATE); 190 spx5_wr(BIT(rx->channel_id), sparx5, FDMA_CH_RELOAD); 196 spx5_wr(BI [all...] |
H A D | sparx5_vcap_impl.c | 216 spx5_wr(VCAP_SUPER_CFG_MV_NUM_POS_SET(0) | 219 spx5_wr(VCAP_SUPER_CTRL_UPDATE_CMD_SET(VCAP_CMD_INITIALIZE) | 230 spx5_wr(VCAP_ES0_CFG_MV_NUM_POS_SET(0) | 233 spx5_wr(VCAP_ES0_CTRL_UPDATE_CMD_SET(VCAP_CMD_INITIALIZE) | 244 spx5_wr(VCAP_ES2_CFG_MV_NUM_POS_SET(0) | 247 spx5_wr(VCAP_ES2_CTRL_UPDATE_CMD_SET(VCAP_CMD_INITIALIZE) | 935 spx5_wr(keystr[idx] & mskstr[idx], sparx5, 937 spx5_wr(~mskstr[idx], sparx5, 943 spx5_wr(actstr[idx], sparx5, 955 spx5_wr(admi [all...] |
H A D | sparx5_mactable.c | 76 spx5_wr(mach, sparx5, LRN_MAC_ACCESS_CFG_0); 77 spx5_wr(macl, sparx5, LRN_MAC_ACCESS_CFG_1); 99 spx5_wr(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(addr) | 104 spx5_wr(0, sparx5, LRN_MAC_ACCESS_CFG_3); 107 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(MAC_CMD_LEARN) | 169 spx5_wr(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(1) | 172 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET 200 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(MAC_CMD_LOOKUP) | 228 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(MAC_CMD_UNLEARN) | 443 spx5_wr(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SE [all...] |
H A D | sparx5_police.c | 29 spx5_wr(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(pup_tokens), sparx5,
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H A D | sparx5_sdlb.c | 244 spx5_wr(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_SET(next) | 249 spx5_wr(ANA_AC_SDLB_XLB_START_LBSET_START_SET(first), sparx5, 327 spx5_wr(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_SET(group->pup_interval), 330 spx5_wr(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_SET(frame_size), 333 spx5_wr(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_SET(thres_shift), sparx5,
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H A D | sparx5_main.c | 410 spx5_wr(ANA_AC_STAT_RESET_RESET_SET(1), sparx5, ANA_AC_STAT_RESET); 411 spx5_wr(ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(1), sparx5, ASM_STAT_CFG); 414 spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1), sparx5, HSCH_RESET_CFG); 554 spx5_wr(0xFFF, sparx5, 558 spx5_wr(0xFFF, sparx5, 563 spx5_wr(QLIM_WM(80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); 564 spx5_wr(QLIM_WM(90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); 565 spx5_wr(QLIM_WM(95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); 566 spx5_wr(QLIM_WM(100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); 591 spx5_wr(sparx [all...] |
H A D | sparx5_ptp.c | 424 spx5_wr((u32)tod_inc & 0xFFFFFFFF, sparx5, 426 spx5_wr((u32)(tod_inc >> 32), sparx5, 457 spx5_wr(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(upper_32_bits(ts->tv_sec)), 459 spx5_wr(lower_32_bits(ts->tv_sec), 461 spx5_wr(ts->tv_nsec, sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN)); 533 spx5_wr(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(delta), 612 spx5_wr(PTP_PTP_DOM_CFG_PTP_ENA_SET(0), sparx5, PTP_PTP_DOM_CFG); 620 spx5_wr((u32)tod_adj & 0xFFFFFFFF, sparx5, 622 spx5_wr((u32)(tod_adj >> 32), sparx5, 631 spx5_wr(PTP_PTP_DOM_CFG_PTP_ENA_SE [all...] |
H A D | sparx5_port.c | 90 spx5_wr(value, sparx5, DEV2G5_PCS1G_STICKY(portno)); 571 spx5_wr(DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(etype) | 756 spx5_wr(DEV2G5_PCS1G_CFG_PCS_ENA_SET(1), 764 spx5_wr(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(abil) | 771 spx5_wr(0, sparx5, DEV2G5_PCS1G_ANEG_CFG(port->portno)); 890 spx5_wr(DEV2G5_MAC_IFG_CFG_TX_IFG_SET(tx_gap) | 903 spx5_wr(DEV2G5_MAC_ENA_CFG_RX_ENA | 1050 spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) | 1067 spx5_wr(QSYS_ATOP_ATOP_SET(atop), 1072 spx5_wr(PAUSE_DISCAR [all...] |
H A D | sparx5_qos.c | 90 spx5_wr(HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(leak_time), sparx5, 252 spx5_wr(HSCH_SE_CONNECT_SE_LEAK_LINK_SET(idx_next), sparx5, 346 spx5_wr(HSCH_CIR_CFG_CIR_RATE_SET(sh->rate) |
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H A D | sparx5_calendar.c | 217 spx5_wr(cal[idx], sparx5, QSYS_CAL_AUTO(idx)); 229 spx5_wr(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(12), 539 spx5_wr(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1), 552 spx5_wr(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(0),
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H A D | sparx5_vcap_debugfs.c | 282 spx5_wr(value, sparx5, ANA_ACL_SEC_LOOKUP_STICKY(lookup)); 433 spx5_wr(value, sparx5, EACL_SEC_LOOKUP_STICKY(lookup));
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H A D | sparx5_main.h | 631 static inline void spx5_wr(u32 val, struct sparx5 *sparx5, function
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H A D | sparx5_ethtool.c | 210 spx5_wr(XQS_STAT_CFG_STAT_VIEW_SET(portno), sparx5, XQS_STAT_CFG); 1171 spx5_wr(XQS_STAT_CFG_STAT_VIEW_SET(portno) |
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