Searched refs:spx5_rmw (Results 1 - 16 of 16) sorted by relevance

/linux-master/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_police.c32 spx5_rmw(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(max_pup_tokens),
36 spx5_rmw(ANA_AC_SDLB_THRES_THRES_SET(thres), ANA_AC_SDLB_THRES_THRES,
H A Dsparx5_port.c352 spx5_rmw(0,
358 spx5_rmw(HSCH_PORT_MODE_DEQUEUE_DIS,
364 spx5_rmw(QSYS_PAUSE_CFG_PAUSE_STOP_SET(0xFFF - 1),
374 spx5_rmw(HSCH_FLUSH_CTRL_FLUSH_PORT_SET(port->portno) |
386 spx5_rmw(0,
422 spx5_rmw(HSCH_FLUSH_CTRL_FLUSH_PORT_SET(port->portno) |
441 spx5_rmw(DEV25G_PCS25G_CFG_PCS25G_ENA_SET(0),
447 spx5_rmw(DEV2G5_PCS1G_CFG_PCS_ENA_SET(0),
529 spx5_rmw(BIT(inst),
536 spx5_rmw(PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SE
[all...]
H A Dsparx5_vlan.c29 spx5_rmw(ANA_L3_VLAN_CTRL_VLAN_ENA_SET(1),
36 spx5_rmw(ANA_L3_VLAN_CFG_VLAN_FID_SET(vid),
47 spx5_rmw(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(0) |
127 spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG(pgid));
131 spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG1(pgid));
135 spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG2(pgid));
234 spx5_rmw(REW_PORT_VLAN_CFG_PORT_VID_SET(port->vid),
H A Dsparx5_fdma.c127 spx5_rmw(FDMA_XTR_CFG_XTR_FIFO_WM_SET(31), FDMA_XTR_CFG_XTR_FIFO_WM,
132 spx5_rmw(FDMA_PORT_CTRL_XTR_STOP_SET(0), FDMA_PORT_CTRL_XTR_STOP,
136 spx5_rmw(BIT(rx->channel_id),
147 spx5_rmw(0, BIT(rx->channel_id) & FDMA_CH_ACTIVATE_CH_ACTIVATE,
151 spx5_rmw(0, BIT(rx->channel_id) & FDMA_INTR_DB_ENA_INTR_DB_ENA,
155 spx5_rmw(FDMA_PORT_CTRL_XTR_STOP_SET(1), FDMA_PORT_CTRL_XTR_STOP,
173 spx5_rmw(FDMA_PORT_CTRL_INJ_STOP_SET(0), FDMA_PORT_CTRL_INJ_STOP,
183 spx5_rmw(0, BIT(tx->channel_id) & FDMA_CH_ACTIVATE_CH_ACTIVATE,
286 spx5_rmw(BIT(rx->channel_id),
511 spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SE
[all...]
H A Dsparx5_ptp.c282 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_SAVE) |
340 spx5_rmw(REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(1),
367 spx5_rmw(REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(1),
420 spx5_rmw(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(1 << BIT(phc->index)),
429 spx5_rmw(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(0),
448 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_IDLE) |
464 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_LOAD) |
487 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_SAVE) |
525 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_IDLE) |
537 spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SE
[all...]
H A Dsparx5_qos.c248 spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(layer),
256 spx5_rmw(HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(se_first),
338 spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(layer),
342 spx5_rmw(HSCH_SE_CFG_SE_FRM_MODE_SET(sh->mode), HSCH_SE_CFG_SE_FRM_MODE,
367 spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(2) |
373 spx5_rmw(HSCH_SE_CFG_SE_DWRR_CNT_SET(dwrr->count),
378 spx5_rmw(HSCH_DWRR_ENTRY_DWRR_COST_SET(dwrr->cost[i]),
H A Dsparx5_psfp.c75 spx5_rmw(ANA_L2_TSN_CFG_TSN_SFID_SET(sfid), ANA_L2_TSN_CFG_TSN_SFID,
78 spx5_rmw(ANA_L2_DLB_CFG_DLB_IDX_SET(fmid), ANA_L2_DLB_CFG_DLB_IDX,
121 spx5_rmw(ANA_AC_TSN_SF_CFG_TSN_SGID_SET(sf->sgid) |
150 spx5_rmw(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(base_msb) |
330 spx5_rmw(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(1),
H A Dsparx5_main.c391 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(1),
396 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(0),
491 spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) |
508 spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100),
513 spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100),
518 spx5_rmw(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100),
523 spx5_rmw(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(clk_period / 100),
529 spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100),
534 spx5_rmw(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET
540 spx5_rmw(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SE
[all...]
H A Dsparx5_packet.c292 spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(1),
324 spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(1),
330 spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(0),
337 spx5_rmw(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(0),
H A Dsparx5_vcap_impl.c1546 spx5_rmw(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_SET(value),
1553 spx5_rmw(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_SET(value),
1560 spx5_rmw(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_SET(value),
1635 spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(value),
1642 spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_SET(value),
1646 spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_SET(value),
1653 spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(value),
1658 spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_SET(value),
1665 spx5_rmw(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(value),
1728 spx5_rmw(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_SE
[all...]
H A Dsparx5_sdlb.c61 spx5_rmw(ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(0),
68 spx5_rmw(ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(1),
H A Dsparx5_calendar.c211 spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(10),
222 spx5_rmw(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(671), /* 672->671 */
234 spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(8),
543 spx5_rmw(DSM_TAXI_CAL_CFG_CAL_IDX_SET(idx),
547 spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(data->schedule[idx]),
H A Dsparx5_mactable.c482 spx5_rmw(LRN_AUTOAGE_CFG_UNIT_SIZE_SET(2) | /* 10 ms */
H A Dsparx5_switchdev.c508 spx5_rmw(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(enable),
H A Dsparx5_main.h651 static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5, function
H A Dsparx5_ethtool.c1162 spx5_rmw(ANA_AC_PORT_SGE_CFG_MASK_SET(0xf0f0),
1176 spx5_rmw(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(1) |

Completed in 220 milliseconds