H A D | sequencer.c | 57 ((non_skip_value) & seq->skip_delay_mask) 74 static void set_failing_group_stage(struct socfpga_sdrseq *seq, argument 81 if (seq->gbl.error_stage == CAL_STAGE_NIL) { 82 seq->gbl.error_substage = substage; 83 seq->gbl.error_stage = stage; 84 seq->gbl.error_group = group; 109 static void phy_mgr_initialize(struct socfpga_sdrseq *seq) argument 131 if ((seq->dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) 134 ratio = seq->rwcfg->mem_dq_per_read_dqs / 135 seq 151 set_rank_and_odt_mask(struct socfpga_sdrseq *seq, const u32 rank, const u32 odt_mode) argument 324 scc_mgr_set_dqs_io_in_delay(struct socfpga_sdrseq *seq, u32 delay) argument 331 scc_mgr_set_dm_in_delay(struct socfpga_sdrseq *seq, u32 dm, u32 delay) argument 344 scc_mgr_set_dqs_out1_delay(struct socfpga_sdrseq *seq, u32 delay) argument 351 scc_mgr_set_dm_out1_delay(struct socfpga_sdrseq *seq, u32 dm, u32 delay) argument 393 scc_mgr_set_all_ranks(struct socfpga_sdrseq *seq, const u32 off, const u32 grp, const u32 val, const int update) argument 410 scc_mgr_set_dqs_en_phase_all_ranks(struct socfpga_sdrseq *seq, u32 read_group, u32 phase) argument 425 scc_mgr_set_dqdqs_output_phase_all_ranks(struct socfpga_sdrseq *seq, u32 write_group, u32 phase) argument 440 scc_mgr_set_dqs_en_delay_all_ranks(struct socfpga_sdrseq *seq, u32 read_group, u32 delay) argument 462 scc_mgr_set_oct_out1_delay(struct socfpga_sdrseq *seq, const u32 write_group, const u32 delay) argument 514 scc_mgr_zero_all(struct socfpga_sdrseq *seq) argument 578 scc_mgr_load_dqs_for_write_group(struct socfpga_sdrseq *seq, const u32 write_group) argument 601 scc_mgr_zero_group(struct socfpga_sdrseq *seq, const u32 write_group, const int out_only) argument 650 scc_mgr_apply_group_dq_in_delay(struct socfpga_sdrseq *seq, u32 group_bgn, u32 delay) argument 669 scc_mgr_apply_group_dq_out1_delay(struct socfpga_sdrseq *seq, const u32 delay) argument 681 scc_mgr_apply_group_dm_out1_delay(struct socfpga_sdrseq *seq, u32 delay1) argument 694 scc_mgr_apply_group_dqs_io_and_oct_out1(struct socfpga_sdrseq *seq, u32 write_group, u32 delay) argument 712 scc_mgr_apply_group_all_out_delay_add(struct socfpga_sdrseq *seq, const u32 write_group, const u32 delay) argument 764 scc_mgr_apply_group_all_out_delay_add_all_ranks(struct socfpga_sdrseq *seq, const u32 write_group, const u32 delay) argument 783 set_jump_as_return(struct socfpga_sdrseq *seq) argument 800 delay_for_n_mem_clocks(struct socfpga_sdrseq *seq, const u32 clocks) argument 874 delay_for_n_ns(struct socfpga_sdrseq *seq, const u32 ns) argument 889 rw_mgr_mem_init_load_regs(struct socfpga_sdrseq *seq, u32 cntr0, u32 cntr1, u32 cntr2, u32 jump) argument 918 rw_mgr_mem_load_user_ddr2(struct socfpga_sdrseq *seq, const int handoff) argument 965 rw_mgr_mem_load_user_ddr3(struct socfpga_sdrseq *seq, const u32 fin1, const u32 fin2, const int precharge) argument 1029 rw_mgr_mem_load_user(struct socfpga_sdrseq *seq, const u32 fin1, const u32 fin2, const int precharge) argument 1045 rw_mgr_mem_initialize(struct socfpga_sdrseq *seq) argument 1129 rw_mgr_mem_handoff(struct socfpga_sdrseq *seq) argument 1148 rw_mgr_mem_calibrate_write_test_issue(struct socfpga_sdrseq *seq, u32 group, u32 test_dm) argument 1293 rw_mgr_mem_calibrate_write_test(struct socfpga_sdrseq *seq, const u32 rank_bgn, const u32 write_group, const u32 use_dm, const u32 all_correct, u32 *bit_chk, const u32 all_ranks) argument 1360 rw_mgr_mem_calibrate_read_test_patterns(struct socfpga_sdrseq *seq, const u32 rank_bgn, const u32 group, const u32 all_ranks) argument 1436 rw_mgr_mem_calibrate_read_load_patterns(struct socfpga_sdrseq *seq, const u32 rank_bgn, const int all_ranks) argument 1495 rw_mgr_mem_calibrate_read_test(struct socfpga_sdrseq *seq, const u32 rank_bgn, const u32 group, const u32 num_tries, const u32 all_correct, u32 *bit_chk, const u32 all_groups, const u32 all_ranks) argument 1611 rw_mgr_mem_calibrate_read_test_all_ranks(struct socfpga_sdrseq *seq, const u32 grp, const u32 num_tries, const u32 all_correct, const u32 all_groups) argument 1639 rw_mgr_decr_vfifo(struct socfpga_sdrseq *seq, const u32 grp) argument 1653 find_vfifo_failing_read(struct socfpga_sdrseq *seq, const u32 grp) argument 1690 sdr_find_phase_delay(struct socfpga_sdrseq *seq, int working, int delay, const u32 grp, u32 *work, const u32 work_inc, u32 *pd) argument 1728 sdr_find_phase(struct socfpga_sdrseq *seq, int working, const u32 grp, u32 *work, u32 *i, u32 *p) argument 1764 sdr_working_phase(struct socfpga_sdrseq *seq, const u32 grp, u32 *work_bgn, u32 *d, u32 *p, u32 *i) argument 1796 sdr_backup_phase(struct socfpga_sdrseq *seq, const u32 grp, u32 *work_bgn, u32 *p) argument 1845 sdr_nonworking_phase(struct socfpga_sdrseq *seq, const u32 grp, u32 *work_end, u32 *p, u32 *i) argument 1876 sdr_find_window_center(struct socfpga_sdrseq *seq, const u32 grp, const u32 work_bgn, const u32 work_end) argument 1949 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(struct socfpga_sdrseq *seq, const u32 grp) argument 2121 search_stop_check(struct socfpga_sdrseq *seq, const int write, const int d, const int rank_bgn, const u32 write_group, const u32 read_group, u32 *bit_chk, u32 *sticky_bit_chk, const u32 use_read_test) argument 2178 search_left_edge(struct socfpga_sdrseq *seq, const int write, const int rank_bgn, const u32 write_group, const u32 read_group, const u32 test_bgn, u32 *sticky_bit_chk, int *left_edge, int *right_edge, const u32 use_read_test) argument 2289 search_right_edge(struct socfpga_sdrseq *seq, const int write, const int rank_bgn, const u32 write_group, const u32 read_group, const int start_dqs, const int start_dqs_en, u32 *sticky_bit_chk, int *left_edge, int *right_edge, const u32 use_read_test) argument 2417 get_window_mid_index(struct socfpga_sdrseq *seq, const int write, int *left_edge, int *right_edge, int *mid_min) argument 2465 center_dq_windows(struct socfpga_sdrseq *seq, const int write, int *left_edge, int *right_edge, const int mid_min, const int orig_mid_min, const int min_index, const int test_bgn, int *dq_margin, int *dqs_margin) argument 2541 rw_mgr_mem_calibrate_vfifo_center(struct socfpga_sdrseq *seq, const u32 rank_bgn, const u32 rw_group, const u32 test_bgn, const int use_read_test, const int update_fom) argument 2689 rw_mgr_mem_calibrate_guaranteed_write(struct socfpga_sdrseq *seq, const u32 rw_group, const u32 phase) argument 2732 rw_mgr_mem_calibrate_dqs_enable_calibration(struct socfpga_sdrseq *seq, const u32 rw_group, const u32 test_bgn) argument 2796 rw_mgr_mem_calibrate_dq_dqs_centering(struct socfpga_sdrseq *seq, const u32 rw_group, const u32 test_bgn, const int use_read_test, const int update_fom) argument 2844 rw_mgr_mem_calibrate_vfifo(struct socfpga_sdrseq *seq, const u32 rw_group, const u32 test_bgn) argument 2944 rw_mgr_mem_calibrate_vfifo_end(struct socfpga_sdrseq *seq, const u32 rw_group, const u32 test_bgn) argument 2975 rw_mgr_mem_calibrate_lfifo(struct socfpga_sdrseq *seq) argument 3043 search_window(struct socfpga_sdrseq *seq, const int search_dm, const u32 rank_bgn, const u32 write_group, int *bgn_curr, int *end_curr, int *bgn_best, int *end_best, int *win_best, int new_dqs) argument 3125 rw_mgr_mem_calibrate_writes_center(struct socfpga_sdrseq *seq, const u32 rank_bgn, const u32 write_group, const u32 test_bgn) argument 3288 rw_mgr_mem_calibrate_writes(struct socfpga_sdrseq *seq, const u32 rank_bgn, const u32 group, const u32 test_bgn) argument 3315 mem_precharge_and_activate(struct socfpga_sdrseq *seq) argument 3347 mem_init_latency(struct socfpga_sdrseq *seq) argument 3388 mem_skip_calibrate(struct socfpga_sdrseq *seq) argument 3479 mem_calibrate(struct socfpga_sdrseq *seq) argument 3666 run_mem_calibrate(struct socfpga_sdrseq *seq) argument 3712 debug_mem_calibrate(struct socfpga_sdrseq *seq, int pass) argument 3783 initialize_reg_file(struct socfpga_sdrseq *seq) argument 3851 initialize_tracking(struct socfpga_sdrseq *seq) argument 3903 struct socfpga_sdrseq seq; local [all...] |