1/* SPDX-License-Identifier: BSD-3-Clause */
2/*
3 * Copyright Altera Corporation (C) 2012-2015
4 */
5
6#ifndef _SEQUENCER_H_
7#define _SEQUENCER_H_
8
9#define RW_MGR_NUM_DM_PER_WRITE_GROUP (seq->rwcfg->mem_data_mask_width \
10	/ seq->rwcfg->mem_if_write_dqs_width)
11#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP ( \
12	seq->rwcfg->true_mem_data_mask_width \
13	/ seq->rwcfg->mem_if_write_dqs_width)
14
15#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (seq->rwcfg->mem_if_read_dqs_width \
16	/ seq->rwcfg->mem_if_write_dqs_width)
17#define NUM_RANKS_PER_SHADOW_REG (seq->rwcfg->mem_number_of_ranks \
18	/ NUM_SHADOW_REGS)
19
20#define RW_MGR_RUN_SINGLE_GROUP_OFFSET		0x0
21#define RW_MGR_RUN_ALL_GROUPS_OFFSET		0x0400
22#define RW_MGR_RESET_READ_DATAPATH_OFFSET	0x1000
23#define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET	0x1400
24#define RW_MGR_INST_ROM_WRITE_OFFSET		0x1800
25#define RW_MGR_AC_ROM_WRITE_OFFSET		0x1C00
26
27#define NUM_SHADOW_REGS			1
28
29#define RW_MGR_RANK_NONE		0xFF
30#define RW_MGR_RANK_ALL			0x00
31
32#define RW_MGR_ODT_MODE_OFF		0
33#define RW_MGR_ODT_MODE_READ_WRITE	1
34
35#define NUM_CALIB_REPEAT		1
36
37#define NUM_READ_TESTS			7
38#define NUM_READ_PB_TESTS		7
39#define NUM_WRITE_TESTS			15
40#define NUM_WRITE_PB_TESTS		31
41
42#define PASS_ALL_BITS			1
43#define PASS_ONE_BIT			0
44
45/* calibration stages */
46#define CAL_STAGE_NIL			0
47#define CAL_STAGE_VFIFO			1
48#define CAL_STAGE_WLEVEL		2
49#define CAL_STAGE_LFIFO			3
50#define CAL_STAGE_WRITES		4
51#define CAL_STAGE_FULLTEST		5
52#define CAL_STAGE_REFRESH		6
53#define CAL_STAGE_CAL_SKIPPED		7
54#define CAL_STAGE_CAL_ABORTED		8
55#define CAL_STAGE_VFIFO_AFTER_WRITES	9
56
57/* calibration substages */
58#define CAL_SUBSTAGE_NIL		0
59#define CAL_SUBSTAGE_GUARANTEED_READ	1
60#define CAL_SUBSTAGE_DQS_EN_PHASE	2
61#define CAL_SUBSTAGE_VFIFO_CENTER	3
62#define CAL_SUBSTAGE_WORKING_DELAY	1
63#define CAL_SUBSTAGE_LAST_WORKING_DELAY	2
64#define CAL_SUBSTAGE_WLEVEL_COPY	3
65#define CAL_SUBSTAGE_WRITES_CENTER	1
66#define CAL_SUBSTAGE_READ_LATENCY	1
67#define CAL_SUBSTAGE_REFRESH		1
68
69#define SCC_MGR_GROUP_COUNTER_OFFSET		0x0000
70#define SCC_MGR_DQS_IN_DELAY_OFFSET		0x0100
71#define SCC_MGR_DQS_EN_PHASE_OFFSET		0x0200
72#define SCC_MGR_DQS_EN_DELAY_OFFSET		0x0300
73#define SCC_MGR_DQDQS_OUT_PHASE_OFFSET		0x0400
74#define SCC_MGR_OCT_OUT1_DELAY_OFFSET		0x0500
75#define SCC_MGR_IO_OUT1_DELAY_OFFSET		0x0700
76#define SCC_MGR_IO_IN_DELAY_OFFSET		0x0900
77
78/* HHP-HPS-specific versions of some commands */
79#define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET	0x0600
80#define SCC_MGR_IO_OE_DELAY_OFFSET		0x0800
81#define SCC_MGR_HHP_GLOBALS_OFFSET		0x0A00
82#define SCC_MGR_HHP_RFILE_OFFSET		0x0B00
83#define SCC_MGR_AFI_CAL_INIT_OFFSET		0x0D00
84
85#define SDR_PHYGRP_SCCGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x0)
86#define SDR_PHYGRP_PHYMGRGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x1000)
87#define SDR_PHYGRP_RWMGRGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x2000)
88#define SDR_PHYGRP_DATAMGRGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x4000)
89#define SDR_PHYGRP_REGFILEGRP_ADDRESS		(SOCFPGA_SDR_ADDRESS | 0x4800)
90
91#define PHY_MGR_CAL_RESET		(0)
92#define PHY_MGR_CAL_SUCCESS		(1)
93#define PHY_MGR_CAL_FAIL		(2)
94
95#define CALIB_SKIP_DELAY_LOOPS		(1 << 0)
96#define CALIB_SKIP_ALL_BITS_CHK		(1 << 1)
97#define CALIB_SKIP_DELAY_SWEEPS		(1 << 2)
98#define CALIB_SKIP_VFIFO		(1 << 3)
99#define CALIB_SKIP_LFIFO		(1 << 4)
100#define CALIB_SKIP_WLEVEL		(1 << 5)
101#define CALIB_SKIP_WRITES		(1 << 6)
102#define CALIB_SKIP_FULL_TEST		(1 << 7)
103#define CALIB_SKIP_ALL			(CALIB_SKIP_VFIFO | \
104				CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \
105				CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
106#define CALIB_IN_RTL_SIM			(1 << 8)
107
108/* Scan chain manager command addresses */
109#define READ_SCC_OCT_OUT2_DELAY			0
110#define READ_SCC_DQ_OUT2_DELAY			0
111#define READ_SCC_DQS_IO_OUT2_DELAY		0
112#define READ_SCC_DM_IO_OUT2_DELAY		0
113
114/* HHP-HPS-specific values */
115#define SCC_MGR_HHP_EXTRAS_OFFSET			0
116#define SCC_MGR_HHP_DQSE_MAP_OFFSET			1
117
118/* PHY Debug mode flag constants */
119#define PHY_DEBUG_IN_DEBUG_MODE 0x00000001
120#define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002
121#define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004
122#define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008
123#define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
124#define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
125
126struct socfpga_sdr_rw_load_manager {
127	u32	load_cntr0;
128	u32	load_cntr1;
129	u32	load_cntr2;
130	u32	load_cntr3;
131};
132
133struct socfpga_sdr_rw_load_jump_manager {
134	u32	load_jump_add0;
135	u32	load_jump_add1;
136	u32	load_jump_add2;
137	u32	load_jump_add3;
138};
139
140struct socfpga_sdr_reg_file {
141	u32 signature;
142	u32 debug_data_addr;
143	u32 cur_stage;
144	u32 fom;
145	u32 failing_stage;
146	u32 debug1;
147	u32 debug2;
148	u32 dtaps_per_ptap;
149	u32 trk_sample_count;
150	u32 trk_longidle;
151	u32 delays;
152	u32 trk_rw_mgr_addr;
153	u32 trk_read_dqs_width;
154	u32 trk_rfsh;
155};
156
157/* parameter variable holder */
158struct param_type {
159	u32	read_correct_mask;
160	u32	read_correct_mask_vg;
161	u32	write_correct_mask;
162	u32	write_correct_mask_vg;
163};
164
165
166/* global variable holder */
167struct gbl_type {
168	uint32_t phy_debug_mode_flags;
169
170	/* current read latency */
171
172	uint32_t curr_read_lat;
173
174	/* error code */
175
176	uint32_t error_substage;
177	uint32_t error_stage;
178	uint32_t error_group;
179
180	/* figure-of-merit in, figure-of-merit out */
181
182	uint32_t fom_in;
183	uint32_t fom_out;
184
185	/*USER Number of RW Mgr NOP cycles between
186	write command and write data */
187	uint32_t rw_wl_nop_cycles;
188};
189
190struct socfpga_sdr_scc_mgr {
191	u32	dqs_ena;
192	u32	dqs_io_ena;
193	u32	dq_ena;
194	u32	dm_ena;
195	u32	__padding1[4];
196	u32	update;
197	u32	__padding2[7];
198	u32	active_rank;
199};
200
201/* PHY manager configuration registers. */
202struct socfpga_phy_mgr_cfg {
203	u32	phy_rlat;
204	u32	reset_mem_stbl;
205	u32	mux_sel;
206	u32	cal_status;
207	u32	cal_debug_info;
208	u32	vfifo_rd_en_ovrd;
209	u32	afi_wlat;
210	u32	afi_rlat;
211};
212
213/* PHY manager command addresses. */
214struct socfpga_phy_mgr_cmd {
215	u32	inc_vfifo_fr;
216	u32	inc_vfifo_hard_phy;
217	u32	fifo_reset;
218	u32	inc_vfifo_fr_hr;
219	u32	inc_vfifo_qr;
220};
221
222struct socfpga_data_mgr {
223	u32	__padding1;
224	u32	t_wl_add;
225	u32	mem_t_add;
226	u32	t_rl_add;
227};
228
229/* This struct describes the controller @ SOCFPGA_SDR_ADDRESS */
230struct socfpga_sdr {
231	/* SDR_PHYGRP_SCCGRP_ADDRESS */
232	u8 _align1[0xe00];
233	/* SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00 */
234	struct socfpga_sdr_scc_mgr sdr_scc_mgr;
235	u8 _align2[0x1bc];
236	/* SDR_PHYGRP_PHYMGRGRP_ADDRESS */
237	struct socfpga_phy_mgr_cmd phy_mgr_cmd;
238	u8 _align3[0x2c];
239	/* SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40 */
240	struct socfpga_phy_mgr_cfg phy_mgr_cfg;
241	u8 _align4[0xfa0];
242	/* SDR_PHYGRP_RWMGRGRP_ADDRESS */
243	u8 rwmgr_grp[0x800];
244	/* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800 */
245	struct socfpga_sdr_rw_load_manager sdr_rw_load_mgr_regs;
246	u8 _align5[0x3f0];
247	/* SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00 */
248	struct socfpga_sdr_rw_load_jump_manager sdr_rw_load_jump_mgr_regs;
249	u8 _align6[0x13f0];
250	/* SDR_PHYGRP_DATAMGRGRP_ADDRESS */
251	struct socfpga_data_mgr data_mgr;
252	u8 _align7[0x7f0];
253	/* SDR_PHYGRP_REGFILEGRP_ADDRESS */
254	struct socfpga_sdr_reg_file sdr_reg_file;
255	u8 _align8[0x7c8];
256	/* SDR_CTRLGRP_ADDRESS */
257	struct socfpga_sdr_ctrl sdr_ctrl;
258	u8 _align9[0xea4];
259};
260
261struct socfpga_sdrseq {
262	const struct socfpga_sdram_rw_mgr_config *rwcfg;
263	const struct socfpga_sdram_io_config *iocfg;
264	const struct socfpga_sdram_misc_config *misccfg;
265	/* calibration steps requested by the rtl */
266	u16 dyn_calib_steps;
267	/*
268	 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
269	 * instead of static, we use boolean logic to select between
270	 * non-skip and skip values
271	 *
272	 * The mask is set to include all bits when not-skipping, but is
273	 * zero when skipping
274	 */
275
276	u16 skip_delay_mask;	/* mask off bits when skipping/not-skipping */
277	struct gbl_type gbl;
278	struct param_type param;
279};
280
281int sdram_calibration_full(struct socfpga_sdr *sdr);
282bool dram_is_ddr(const u8 ddr);
283
284#endif /* _SEQUENCER_H_ */
285