Searched refs:sclk (Results 1 - 25 of 157) sorted by relevance

1234567

/linux-master/drivers/clk/hisilicon/
H A Dclkgate-separated.c34 struct clkgate_separated *sclk; local
38 sclk = container_of(hw, struct clkgate_separated, hw);
39 if (sclk->lock)
40 spin_lock_irqsave(sclk->lock, flags);
41 reg = BIT(sclk->bit_idx);
42 writel_relaxed(reg, sclk->enable);
43 readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS);
44 if (sclk->lock)
45 spin_unlock_irqrestore(sclk->lock, flags);
51 struct clkgate_separated *sclk; local
67 struct clkgate_separated *sclk; local
89 struct clkgate_separated *sclk; local
[all...]
/linux-master/drivers/clk/meson/
H A Dsclk-div.c23 #include "sclk-div.h"
31 static int sclk_div_maxval(struct meson_sclk_div_data *sclk) argument
33 return (1 << sclk->div.width) - 1;
36 static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk) argument
38 return sclk_div_maxval(sclk) + 1;
51 struct meson_sclk_div_data *sclk)
61 maxdiv = sclk_div_maxdiv(sclk);
92 bestdiv = sclk_div_maxdiv(sclk);
103 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); local
106 div = sclk_div_bestdiv(hw, req->rate, &req->best_parent_rate, sclk);
49 sclk_div_bestdiv(struct clk_hw *hw, unsigned long rate, unsigned long *prate, struct meson_sclk_div_data *sclk) argument
112 sclk_apply_ratio(struct clk_regmap *clk, struct meson_sclk_div_data *sclk) argument
129 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); local
143 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); local
158 sclk_apply_divider(struct clk_regmap *clk, struct meson_sclk_div_data *sclk) argument
171 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); local
186 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); local
194 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); local
204 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); local
212 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); local
223 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); local
[all...]
/linux-master/drivers/clk/
H A Dclk-scmi.c197 static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk, argument
205 .num_parents = sclk->info->num_parents,
207 .name = sclk->info->name,
208 .parent_data = sclk->parent_data,
211 sclk->hw.init = &init;
212 ret = devm_clk_hw_register(dev, &sclk->hw);
216 if (sclk->info->rate_discrete) {
217 int num_rates = sclk->info->list.num_rates;
222 min_rate = sclk->info->list.rates[0];
223 max_rate = sclk
270 struct scmi_clk *sclk; local
[all...]
H A Dclk-scpi.c139 struct scpi_clk *sclk, const char *name)
149 sclk->hw.init = &init;
150 sclk->scpi_ops = get_scpi_ops();
153 sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id);
154 if (IS_ERR(sclk->info))
155 return PTR_ERR(sclk->info);
157 if (sclk->scpi_ops->clk_get_range(sclk
138 scpi_clk_ops_init(struct device *dev, const struct of_device_id *match, struct scpi_clk *sclk, const char *name) argument
177 struct scpi_clk *sclk; local
213 struct scpi_clk *sclk; local
[all...]
H A Dclk-nomadik.c305 struct clk_src *sclk = to_src(hw); local
306 u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0;
307 u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
309 writel(sclk->clkbit, src_base + enreg);
311 while (!(readl(src_base + sreg) & sclk->clkbit))
318 struct clk_src *sclk = to_src(hw); local
319 u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0;
320 u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
322 writel(sclk->clkbit, src_base + disreg);
324 while (readl(src_base + sreg) & sclk
330 struct clk_src *sclk = to_src(hw); local
356 struct clk_src *sclk; local
[all...]
/linux-master/drivers/clk/ralink/
H A Dclk-mt7621.c134 struct mt7621_gate *sclk)
145 .parent_names = &sclk->parent_name,
147 .name = sclk->name,
150 sclk->hw.init = &init;
151 return devm_clk_hw_register(dev, &sclk->hw);
159 struct mt7621_gate *sclk; local
163 sclk = &mt7621_gates[i];
164 sclk->priv = priv;
165 ret = mt7621_gate_ops_init(dev, sclk);
167 dev_err(dev, "Couldn't register clock %s\n", sclk
133 mt7621_gate_ops_init(struct device *dev, struct mt7621_gate *sclk) argument
204 struct mt7621_fixed_clk *sclk; local
322 struct mt7621_clk *sclk; local
397 struct mt7621_clk *sclk = &mt7621_clks_base[i]; local
551 struct mt7621_gate *sclk = &mt7621_gates[i]; local
558 struct mt7621_fixed_clk *sclk = &mt7621_fixed_clks[i]; local
[all...]
H A Dclk-mtmips.c231 struct mtmips_clk *sclk; local
239 sclk = &priv->data->clk_periph[i];
240 ret = of_clk_hw_register(np, &sclk->hw);
246 hws[idx] = &sclk->hw;
253 sclk = &priv->data->clk_periph[i];
254 clk_hw_unregister(&sclk->hw);
283 struct mtmips_clk_fixed *sclk; local
290 sclk = &priv->data->clk_fixed[i];
291 sclk->hw = clk_hw_register_fixed_rate(NULL, sclk
334 struct mtmips_clk_factor *sclk; local
721 struct mtmips_clk *sclk; local
954 struct mtmips_clk *sclk = &priv->data->clk_periph[i]; local
961 struct mtmips_clk_factor *sclk = &priv->data->clk_factor[i]; local
968 struct mtmips_clk_fixed *sclk = &priv->data->clk_fixed[i]; local
975 struct mtmips_clk *sclk = &priv->data->clk_base[i]; local
[all...]
/linux-master/sound/soc/codecs/
H A Drl6231.h30 int rl6231_get_clk_info(int sclk, int rate);
/linux-master/drivers/power/reset/
H A Dat91-poweroff.c55 struct clk *sclk; member in struct:shdwc
162 at91_shdwc.sclk = devm_clk_get(&pdev->dev, NULL);
163 if (IS_ERR(at91_shdwc.sclk))
164 return PTR_ERR(at91_shdwc.sclk);
166 ret = clk_prepare_enable(at91_shdwc.sclk);
201 clk_disable_unprepare(at91_shdwc.sclk);
213 clk_disable_unprepare(at91_shdwc.sclk);
H A Dat91-reset.c73 * @sclk: slow clock
85 struct clk *sclk; member in struct:at91_reset
378 reset->sclk = devm_clk_get(&pdev->dev, NULL);
379 if (IS_ERR(reset->sclk))
380 return PTR_ERR(reset->sclk);
382 ret = clk_prepare_enable(reset->sclk);
416 clk_disable_unprepare(reset->sclk);
425 clk_disable_unprepare(reset->sclk);
H A Dat91-sama5d2_shdwc.c94 struct clk *sclk; member in struct:shdwc
358 at91_shdwc->sclk = devm_clk_get(&pdev->dev, NULL);
359 if (IS_ERR(at91_shdwc->sclk))
360 return PTR_ERR(at91_shdwc->sclk);
362 ret = clk_prepare_enable(at91_shdwc->sclk);
419 clk_disable_unprepare(at91_shdwc->sclk);
439 clk_disable_unprepare(shdw->sclk);
/linux-master/drivers/clk/microchip/
H A Dclk-core.c774 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); local
777 div = (readl(sclk->slew_reg) >> SLEW_SYSDIV_SHIFT) & SLEW_SYSDIV;
792 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); local
799 spin_lock_irqsave(&sclk->core->reg_lock, flags);
802 v = readl(sclk->slew_reg);
808 writel(v, sclk->slew_reg);
811 err = readl_poll_timeout_atomic(sclk->slew_reg, v,
814 spin_unlock_irqrestore(&sclk->core->reg_lock, flags);
821 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); local
824 v = (readl(sclk
837 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); local
887 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); local
930 struct pic32_sys_clk *sclk; local
[all...]
/linux-master/drivers/clocksource/
H A Dtimer-atmel-st.c185 struct clk *sclk; local
216 sclk = of_clk_get(node, 0);
217 if (IS_ERR(sclk)) {
219 return PTR_ERR(sclk);
222 ret = clk_prepare_enable(sclk);
228 sclk_rate = clk_get_rate(sclk);
/linux-master/drivers/gpu/drm/radeon/
H A Drv730_dpm.c39 RV770_SMC_SCLK_VALUE *sclk)
106 sclk->sclk_value = cpu_to_be32(engine_clock);
107 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
108 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
109 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
110 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum);
111 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2);
302 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
303 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
304 table->ACPIState.levels[0].sclk
37 rv730_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, RV770_SMC_SCLK_VALUE *sclk) argument
[all...]
H A Drv770_dpm.c273 a_n = (int)state->medium.sclk * pi->lmp +
274 (int)state->low.sclk * (R600_AH_DFLT - pi->rlp);
275 a_d = (int)state->low.sclk * (100 - (int)pi->rlp) +
276 (int)state->medium.sclk * pi->lmp;
281 a_n = (int)state->high.sclk * pi->lhp + (int)state->medium.sclk *
283 a_d = (int)state->medium.sclk * (100 - (int)pi->rmp) +
284 (int)state->high.sclk * pi->lhp;
487 RV770_SMC_SCLK_VALUE *sclk)
557 sclk
485 rv770_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, RV770_SMC_SCLK_VALUE *sclk) argument
2182 u32 sclk, mclk; local
[all...]
H A Drv740_dpm.c120 RV770_SMC_SCLK_VALUE *sclk)
175 sclk->sclk_value = cpu_to_be32(engine_clock);
176 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
177 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
178 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
179 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum);
180 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2);
385 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
386 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
387 table->ACPIState.levels[0].sclk
119 rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, RV770_SMC_SCLK_VALUE *sclk) argument
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk104.c68 u32 sclk; local
77 sclk = device->crystal;
81 sclk = read_pll(clk, 0x132020);
85 sclk = read_div(clk, 0, 0x137320, 0x137330);
92 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
101 sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13);
102 return sclk / (M * P);
121 u32 sclk local
149 u32 sclk, sdiv; local
236 u32 sclk; local
[all...]
H A Dgf100.c67 u32 sclk; local
75 sclk = device->crystal;
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc);
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref);
88 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140);
94 return sclk * N / M / P;
102 u32 sclk, sctl, sdiv = 2; local
112 sclk = read_vco(clk, dsrc + (doff * 4));
126 return (sclk * 2) / sdiv;
138 u32 sclk, sdi local
223 u32 sclk; local
[all...]
/linux-master/drivers/net/ethernet/marvell/octeontx2/af/
H A Dptp.h29 void ptp_start(struct rvu *rvu, u64 sclk, u32 ext_clk_freq, u32 extts);
/linux-master/sound/soc/intel/skylake/
H A Dskl-nhlt.c90 * sclk/sclkfs.
98 struct skl_ssp_clk *sclk, *sclkfs; local
108 sclk = &ssp_clks[SKL_SCLK_OFS];
129 * But the sclk rate will be generated for the total
153 /* check if the rate is added already to the given SSP's sclk */
155 (sclk[id].rate_cfg[j].rate != 0); j++) {
156 if (sclk[id].rate_cfg[j].rate == rate) {
162 /* Fill rate and parent for sclk/sclkfs */
192 sclk[id].rate_cfg[rate_index].rate = rate;
193 sclk[i
[all...]
/linux-master/sound/soc/meson/
H A Daxg-tdm-formatter.c20 struct clk *sclk; member in struct:axg_tdm_formatter
109 * If sclk is inverted, it means the bit should latched on the
114 ret = clk_set_phase(formatter->sclk, invert ? 0 : 180);
126 ret = clk_prepare_enable(formatter->sclk);
132 clk_disable_unprepare(formatter->sclk);
151 clk_disable_unprepare(formatter->sclk);
208 ret = clk_set_parent(formatter->sclk_sel, ts->iface->sclk);
298 formatter->sclk = devm_clk_get(dev, "sclk");
299 if (IS_ERR(formatter->sclk))
[all...]
/linux-master/drivers/gpu/drm/armada/
H A Darmada_510.c96 * This gets called with sclk = NULL to test whether the mode is
97 * supportable, and again with sclk != NULL to set the clocks up for
102 const struct drm_display_mode *mode, uint32_t *sclk)
119 if (sclk) {
122 *sclk = res.div | armada510_clk_sels[idx];
101 armada510_crtc_compute_clock(struct armada_crtc *dcrtc, const struct drm_display_mode *mode, uint32_t *sclk) argument
/linux-master/drivers/watchdog/
H A Dmarvell_gti_wdt.c78 struct clk *sclk; member in struct:gti_wdt_priv
217 priv->sclk = devm_clk_get_enabled(&pdev->dev, NULL);
218 if (IS_ERR(priv->sclk))
219 return PTR_ERR(priv->sclk);
222 gti_clk_disable_unprepare, priv->sclk);
226 priv->clock_freq = clk_get_rate(priv->sclk);
/linux-master/sound/soc/cirrus/
H A Dep93xx-i2s.c76 struct clk *sclk; member in struct:ep93xx_i2s_info
116 clk_prepare_enable(info->sclk);
161 clk_disable_unprepare(info->sclk);
354 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
358 err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv);
474 info->sclk = clk_get(&pdev->dev, "sclk");
475 if (IS_ERR(info->sclk)) {
476 err = PTR_ERR(info->sclk);
502 clk_put(info->sclk);
[all...]
/linux-master/drivers/media/dvb-frontends/
H A Dcx24110.c544 s32 afc; unsigned sclk; local
548 sclk = cx24110_readreg (state, 0x07) & 0x03;
551 if (sclk==0) sclk=90999000L/2L;
552 else if (sclk==1) sclk=60666000L;
553 else if (sclk==2) sclk=80888000L;
554 else sclk=90999000L;
555 sclk>>
[all...]

Completed in 264 milliseconds

1234567