Searched refs:s10 (Results 1 - 25 of 32) sorted by relevance

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/linux-master/drivers/clk/socfpga/
H A DMakefile4 obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-s10.o \
5 clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o \
/linux-master/drivers/media/rc/img-ir/
H A Dimg-ir-rc5.c62 .s10 = {
H A Dimg-ir-hw.h92 * @s10: Zero symbol timing data for secondary (no leader symbol) decoder
97 struct img_ir_symbol_timing ldr, s00, s01, s10, s11; member in struct:img_ir_timings
120 * @s10: Zero symbol timing register value for secondary decoder
125 u32 ldr, s00, s01, s10, s11, ft; member in struct:img_ir_timing_regvals
H A Dimg-ir-sharp.c83 .s10 = {
H A Dimg-ir-hw.c90 img_ir_symbol_timing_preprocess(&timings->s10, unit);
92 /* default s10 and s11 to s00 and s01 if no leader */
122 img_ir_symbol_timing_defaults(&timings->s10, &defaults->s10);
303 regs->s10 = img_ir_symbol_timing(&timings->s10, tolerance, clock_hz,
386 img_ir_write(priv, IMG_IR_S10_SYMB_TIMING, regs->s10);
390 regs->ldr, regs->s00, regs->s01, regs->s10, regs->s11, ft);
/linux-master/arch/riscv/include/asm/
H A Dcompat.h66 compat_ulong_t s10; member in struct:compat_user_regs_struct
103 cregs->s10 = (compat_ulong_t) regs->s10;
140 regs->s10 = (unsigned long) cregs->s10;
H A Dptrace.h42 unsigned long s10; member in struct:pt_regs
H A Dassembler.h58 REG_L s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0) variable
H A Dkvm_host.h142 unsigned long s10; member in struct:kvm_cpu_context
/linux-master/arch/riscv/include/uapi/asm/
H A Dptrace.h51 unsigned long s10; member in struct:user_regs_struct
/linux-master/arch/riscv/kernel/
H A Dcrash_save_regs.S39 REG_S s10, PT_S10(a0) /* x26 */
H A Dkexec_relocate.S123 mv s10, zero
187 mv s10, zero
H A Dsuspend_entry.S42 REG_S s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
H A Dentry.S303 REG_S s10, TASK_THREAD_S10_RA(a3)
320 REG_L s10, TASK_THREAD_S10_RA(a4)
H A Dprocess.c85 pr_cont(" s8 : " REG_FMT " s9 : " REG_FMT " s10: " REG_FMT "\n",
86 regs->s8, regs->s9, regs->s10);
H A Dptrace.c229 REG_OFFSET_NAME(s10),
H A Dasm-offsets.c98 OFFSET(PT_S10, pt_regs, s10);
155 OFFSET(KVM_ARCH_GUEST_S10, kvm_vcpu_arch, guest_context.s10);
192 OFFSET(KVM_ARCH_HOST_S10, kvm_vcpu_arch, host_context.s10);
/linux-master/arch/riscv/crypto/
H A Dchacha-riscv64-zvkb.S73 #define NONCE1 s10
154 sd s10, 80(sp)
290 ld s10, 80(sp)
/linux-master/tools/testing/selftests/kvm/include/riscv/
H A Dprocessor.h79 unsigned long s10; member in struct:ex_regs
/linux-master/arch/riscv/kvm/
H A Dvcpu_switch.S41 REG_S s10, (KVM_ARCH_HOST_S10)(a0)
101 REG_L s10, (KVM_ARCH_GUEST_S10)(a0)
145 REG_S s10, (KVM_ARCH_GUEST_S10)(a0)
206 REG_L s10, (KVM_ARCH_HOST_S10)(a0)
/linux-master/tools/testing/selftests/kvm/lib/riscv/
H A Dprocessor.c250 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s10), &core.regs.s10);
279 core.regs.s8, core.regs.s9, core.regs.s10, core.regs.s11);
/linux-master/arch/arm/crypto/
H A Dblake2b-neon-core.S70 s8, s9, s10, s11, s12, s13, s14, s15, final=0
160 vadd.u64 d1, d1, M_\s10
H A Dblake2s-core.S129 s8, s9, s10, s11, s12, s13, s14, s15
155 \s8, \s9, \s10, \s11
/linux-master/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler_gfx10.asm598 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0]
625 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0]
1144 s_movreld_b64 s10, s10
H A Dcwsr_trap_handler_gfx8.asm325 s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0]
601 s_movreld_b64 s10, s10

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