Searched refs:rtw_write32_mask (Results 1 - 16 of 16) sorted by last modified time

/linux-master/drivers/net/wireless/realtek/rtw88/
H A Drtw8723d.c105 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL,
150 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);
151 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20);
301 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f);
302 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
307 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
313 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb);
314 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
319 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
322 rtw_write32_mask(rtwde
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H A Drtw8723x.c350 rtw_write32_mask(rtwdev, txagc->addr, txagc->mask, pwr_index);
386 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 1);
387 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 1);
388 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KEEP, 1);
389 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KEEP, 1);
427 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 1);
428 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 0);
429 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 1);
430 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 0);
431 rtw_write32_mask(rtwde
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H A Drtw8723x.h466 rtw_write32_mask(rtwdev, REG_PAD_CTRL1, BIT_BT_BTG_SEL, 0x1);
498 rtw_write32_mask(rtwdev, REG_LTECOEX_PATH_CONTROL,
H A Drtw8703b.c669 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL,
729 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);
730 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20);
757 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f);
758 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
763 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
771 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb);
772 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
777 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
780 rtw_write32_mask(rtwde
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H A Dpci.c1294 rtw_write32_mask(rtwdev, REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1, 1);
1442 rtw_write32_mask(rtwdev, REG_HCI_MIX_CFG,
1505 rtw_write32_mask(rtwdev, REG_ANAPARSW_MAC_0, BIT_CF_L_V2, 0x1);
H A Dmain.c929 rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type);
934 rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid);
2328 rtw_write32_mask(rtwdev, reg2->addr, reg2->mask, v1);
2329 rtw_write32_mask(rtwdev, reg1->addr, reg1->mask, v2);
H A Dmac80211.c348 rtw_write32_mask(rtwdev, edca_param, BIT_MASK_TXOP_LMT, params->txop);
349 rtw_write32_mask(rtwdev, edca_param, BIT_MASK_CWMAX, ecw_max);
350 rtw_write32_mask(rtwdev, edca_param, BIT_MASK_CWMIN, ecw_min);
351 rtw_write32_mask(rtwdev, edca_param, BIT_MASK_AIFS, aifs);
H A Drtw8821c.c189 rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap);
190 rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap);
191 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0);
289 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, BTG_CCA);
290 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, BTG_LNA);
295 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, WLG_CCA);
296 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, WLG_LNA);
365 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
366 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
367 rtw_write32_mask(rtwde
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H A Dphy.c128 rtw_write32_mask(rtwdev,
132 rtw_write32_mask(rtwdev,
236 rtw_write32_mask(rtwdev, dig_cck->addr, dig_cck->mask, igi >> 1);
242 rtw_write32_mask(rtwdev, addr, mask, igi);
1023 rtw_write32_mask(rtwdev, direct_addr, mask, data);
1751 rtw_write32_mask(rtwdev, 0x1e24, BIT(17), 0x1);
1752 rtw_write32_mask(rtwdev, 0x1cd0, BIT(28), 0x1);
1753 rtw_write32_mask(rtwdev, 0x1cd0, BIT(29), 0x1);
1754 rtw_write32_mask(rtwdev, 0x1cd0, BIT(30), 0x1);
1755 rtw_write32_mask(rtwde
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H A Drtw8821c.h110 rtw_write32_mask(rtwdev, addr, mask, data);
111 rtw_write32_mask(rtwdev, addr + 0x200, mask, data);
H A Drtw8822c.c379 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff);
380 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2);
381 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3);
383 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0);
384 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0);
389 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0);
390 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3);
418 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0);
523 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0);
524 rtw_write32_mask(rtwde
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H A Drtw8822b.h110 rtw_write32_mask(rtwdev, addr, mask, data);
111 rtw_write32_mask(rtwdev, addr + 0x200, mask, data);
H A Drtw8822b.c88 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3);
89 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0);
90 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1);
93 rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30);
94 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3);
97 rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f);
98 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3);
170 rtw_write32_mask(rtwdev, 0x24, 0x7e000000, crystal_cap);
171 rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap);
478 rtw_write32_mask(rtwde
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H A Dbf.c376 rtw_write32_mask(rtwdev, REG_BBPSF_CTRL, BIT_MASK_CSI_RATE,
H A Dhci.h227 rtw_write32_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data) function
H A Defuse.c16 rtw_write32_mask(rtwdev, REG_LDO_EFUSE_CTRL, BIT_MASK_EFUSE_BANK_SEL,
130 rtw_write32_mask(rtwdev, REG_EFUSE_CTRL, 0x3ff00, addr);

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