Searched refs:rtsx_add_cmd (Results 1 - 9 of 9) sorted by relevance
/linux-master/drivers/staging/rts5208/ |
H A D | spi.c | 89 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, SPI_RDSR); 90 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 92 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 115 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 116 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 118 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 120 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 143 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 144 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 146 rtsx_add_cmd(chi [all...] |
H A D | xd.c | 74 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd); 75 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 77 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, 81 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0); 103 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0); 104 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)addr); 105 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 107 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3, 109 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF, 116 rtsx_add_cmd(chi [all...] |
H A D | sd.c | 134 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx); 135 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24)); 136 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16)); 137 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8)); 138 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg); 140 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type); 141 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 143 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 145 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, 152 rtsx_add_cmd(chi [all...] |
H A D | rtsx_card.c | 665 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); 666 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0xFF, (div << 4) | mcu_cnt); 667 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); 668 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL2, ssc_depth_mask, ssc_depth); 669 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); 670 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); 672 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, 674 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, 826 rtsx_add_cmd(chip, WRITE_REG_CMD, IRQSTAT0, DMA_DONE_INT, DMA_DONE_INT); 828 rtsx_add_cmd(chi [all...] |
H A D | ms.c | 50 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 51 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 52 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 53 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 56 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 58 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 61 rtsx_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0); 118 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 119 rtsx_add_cmd(chip, WRITE_REG_CMD, 121 rtsx_add_cmd(chi [all...] |
H A D | rtsx_transport.h | 34 void rtsx_add_cmd(struct rtsx_chip *chip, u8 cmd_type, u16 reg_addr, u8 mask,
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H A D | rtsx_chip.c | 2032 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0); 2046 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0); 2074 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, 2088 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
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H A D | rtsx_transport.c | 193 void rtsx_add_cmd(struct rtsx_chip *chip, function
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H A D | rtsx_scsi.c | 1749 rtsx_add_cmd(chip, cmd_type, addr, mask, value);
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