staging/rts5208/xd.c

74 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd);
75 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
77 	rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
81 		rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0);
103 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0);
104 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)addr);
105 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2,
107 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3,
109 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
116 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, (u8)addr);
117 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1,
119 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2,
121 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
140 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
142 	rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
146 		rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_PAGE_STATUS + i),
149 		rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_RESERVED0 + i),
151 	rtsx_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0);
179 		rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i,
206 	rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
208 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
209 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
212 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
214 	rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
299 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
301 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
303 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
305 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
307 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
309 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
313 			rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1,
315 			rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2,
317 			rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3,
319 			rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4,
328 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
329 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
330 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x4B);
331 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
338 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
340 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
342 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
344 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
346 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
348 		rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
352 			rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1,
354 			rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2,
356 			rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3,
358 			rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4,
444 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF,
452 		rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
458 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_INIT,
461 	rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
479 			rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
509 			rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
516 	rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, XD_OUTPUT_EN);
517 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN);
534 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DTCTL, 0xFF,
537 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CATCTL, 0xFF,
542 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
544 		rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
547 		rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
548 		rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
1000 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1001 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_LATER_BBLK);
1002 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, 0xFF);
1003 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, 0xFF);
1004 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_H, 0xFF, 0xFF);
1005 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_L, 0xFF, 0xFF);
1006 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED0, 0xFF, 0xFF);
1007 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED1, 0xFF, 0xFF);
1008 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED2, 0xFF, 0xFF);
1009 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED3, 0xFF, 0xFF);
1015 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF,
1018 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1020 	rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1054 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, 0xFF);
1055 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, 0xFF);
1056 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H,
1058 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)logoff);
1064 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG,
1067 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT,
1070 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
1072 	rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1129 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1130 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1132 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1134 		rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1179 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1180 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1182 		rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1214 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
1216 	rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1218 	rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1219 	rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
1249 		rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1251 		rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1253 		rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1478 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, cmd);
1479 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1481 	rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1529 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_PPB_TO_SIE, XD_PPB_TO_SIE);
1530 	rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
1531 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1532 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1538 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1540 	rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1721 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H,
1723 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)log_off);
1724 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_GBLK);
1725 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1729 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM,
1731 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1732 	rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
1737 	rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
1739 	rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,