Searched refs:reset_ctl (Results 1 - 8 of 8) sorted by relevance

/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsmu_v13_0_10.c32 static bool smu_v13_0_10_is_mode2_default(struct amdgpu_reset_control *reset_ctl) argument
34 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
42 smu_v13_0_10_get_reset_handler(struct amdgpu_reset_control *reset_ctl, argument
46 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
50 for_each_handler(i, handler, reset_ctl) {
56 if (smu_v13_0_10_is_mode2_default(reset_ctl) &&
58 for_each_handler(i, handler, reset_ctl) {
98 smu_v13_0_10_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl, argument
102 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
118 struct amdgpu_reset_control *reset_ctl local
132 smu_v13_0_10_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, struct amdgpu_reset_context *reset_context) argument
230 smu_v13_0_10_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl, struct amdgpu_reset_context *reset_context) argument
281 struct amdgpu_reset_control *reset_ctl; local
[all...]
H A Dsienna_cichlid.c34 static bool sienna_cichlid_is_mode2_default(struct amdgpu_reset_control *reset_ctl) argument
37 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
47 sienna_cichlid_get_reset_handler(struct amdgpu_reset_control *reset_ctl, argument
54 for_each_handler(i, handler, reset_ctl) {
60 if (sienna_cichlid_is_mode2_default(reset_ctl)) {
61 for_each_handler(i, handler, reset_ctl) {
99 sienna_cichlid_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl, argument
103 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
119 struct amdgpu_reset_control *reset_ctl = local
121 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl
141 sienna_cichlid_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, struct amdgpu_reset_context *reset_context) argument
235 sienna_cichlid_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl, struct amdgpu_reset_context *reset_context) argument
290 struct amdgpu_reset_control *reset_ctl; local
[all...]
H A Damdgpu_reset.h48 int (*prepare_env)(struct amdgpu_reset_control *reset_ctl,
50 int (*prepare_hwcontext)(struct amdgpu_reset_control *reset_ctl,
52 int (*perform_reset)(struct amdgpu_reset_control *reset_ctl,
54 int (*restore_hwcontext)(struct amdgpu_reset_control *reset_ctl,
56 int (*restore_env)(struct amdgpu_reset_control *reset_ctl,
71 struct amdgpu_reset_control *reset_ctl,
147 #define for_each_handler(i, handler, reset_ctl) \
149 (handler = (*reset_ctl->reset_handlers)[i]); \
H A Daldebaran.c34 static bool aldebaran_is_mode2_default(struct amdgpu_reset_control *reset_ctl) argument
36 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
46 aldebaran_get_reset_handler(struct amdgpu_reset_control *reset_ctl, argument
50 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
54 if (aldebaran_is_mode2_default(reset_ctl))
63 for_each_handler(i, handler, reset_ctl) {
104 aldebaran_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl, argument
108 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
121 struct amdgpu_reset_control *reset_ctl = local
123 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl
144 aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, struct amdgpu_reset_context *reset_context) argument
328 aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl, struct amdgpu_reset_context *reset_context) argument
426 struct amdgpu_reset_control *reset_ctl; local
[all...]
/linux-master/drivers/net/dsa/realtek/
H A Drtl83xx.c187 priv->reset_ctl = devm_reset_control_get_optional(dev, NULL);
188 if (IS_ERR(priv->reset_ctl)) {
189 ret = PTR_ERR(priv->reset_ctl);
191 return ERR_CAST(priv->reset_ctl);
202 if (priv->reset_ctl || priv->reset) {
310 ret = reset_control_assert(priv->reset_ctl);
323 ret = reset_control_deassert(priv->reset_ctl);
H A Drealtek.h52 struct reset_control *reset_ctl; member in struct:realtek_priv
/linux-master/drivers/gpu/drm/mediatek/
H A Dmtk_disp_merge.c70 struct reset_control *reset_ctl; member in struct:mtk_disp_merge
107 reset_control_reset(priv->reset_ctl);
337 priv->reset_ctl = devm_reset_control_get_optional_exclusive(dev, NULL);
338 if (IS_ERR(priv->reset_ctl))
339 return PTR_ERR(priv->reset_ctl);
H A Dmtk_ethdr.c82 struct reset_control *reset_ctl; member in struct:mtk_ethdr
251 reset_control_reset(priv->reset_ctl);
334 priv->reset_ctl = devm_reset_control_array_get_optional_exclusive(dev);
335 if (IS_ERR(priv->reset_ctl)) {
336 dev_err_probe(dev, PTR_ERR(priv->reset_ctl), "cannot get ethdr reset control\n");
337 return PTR_ERR(priv->reset_ctl);

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