amd/amdgpu/sienna_cichlid.c

34 static bool sienna_cichlid_is_mode2_default(struct amdgpu_reset_control *reset_ctl)
37 	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
47 sienna_cichlid_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
54 		for_each_handler(i, handler, reset_ctl)	{
60 	if (sienna_cichlid_is_mode2_default(reset_ctl)) {
61 		for_each_handler(i, handler, reset_ctl)	{
99 sienna_cichlid_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,
103 	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
119 	struct amdgpu_reset_control *reset_ctl =
121 	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
124 	for_each_handler(i, handler, reset_ctl)	{
125 		if (handler->reset_method == reset_ctl->active_reset) {
141 sienna_cichlid_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,
144 	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
235 sienna_cichlid_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,
239 	struct amdgpu_device *tmp_adev = (struct amdgpu_device *)reset_ctl->handle;
290 	struct amdgpu_reset_control *reset_ctl;
292 	reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL);
293 	if (!reset_ctl)
296 	reset_ctl->handle = adev;
297 	reset_ctl->async_reset = sienna_cichlid_async_reset;
298 	reset_ctl->active_reset = AMD_RESET_METHOD_NONE;
299 	reset_ctl->get_reset_handler = sienna_cichlid_get_reset_handler;
301 	INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset);
303 	reset_ctl->reset_handlers = &sienna_cichlid_rst_handlers;
304 	adev->reset_cntl = reset_ctl;