amd/amdgpu/smu_v13_0_10.c

32 static bool smu_v13_0_10_is_mode2_default(struct amdgpu_reset_control *reset_ctl)
34 	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
42 smu_v13_0_10_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
46 	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
50 		for_each_handler(i, handler, reset_ctl) {
56 	if (smu_v13_0_10_is_mode2_default(reset_ctl) &&
58 		for_each_handler(i, handler, reset_ctl)	{
98 smu_v13_0_10_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,
102 	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
118 	struct amdgpu_reset_control *reset_ctl =
120 	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
123 	for_each_handler(i, handler, reset_ctl)	{
124 		if (handler->reset_method == reset_ctl->active_reset) {
132 smu_v13_0_10_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,
135 	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
230 smu_v13_0_10_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,
234 	struct amdgpu_device *tmp_adev = (struct amdgpu_device *)reset_ctl->handle;
281 	struct amdgpu_reset_control *reset_ctl;
283 	reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL);
284 	if (!reset_ctl)
287 	reset_ctl->handle = adev;
288 	reset_ctl->async_reset = smu_v13_0_10_async_reset;
289 	reset_ctl->active_reset = AMD_RESET_METHOD_NONE;
290 	reset_ctl->get_reset_handler = smu_v13_0_10_get_reset_handler;
292 	INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset);
294 	reset_ctl->reset_handlers = &smu_v13_0_10_rst_handlers;
296 	adev->reset_cntl = reset_ctl;