Searched refs:reg_name (Results 1 - 25 of 290) sorted by relevance

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/linux-master/drivers/regulator/
H A Dregnl.h11 int reg_generate_netlink_event(const char *reg_name, u64 event);
H A Devent.c30 int reg_generate_netlink_event(const char *reg_name, u64 event) argument
64 strscpy(edata->reg_name, reg_name, sizeof(edata->reg_name));
/linux-master/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.h37 #define REG_OFFSET(reg_name) (BASE(mm##reg_name##_BASE_IDX) + mm##reg_name)
39 #define FD_SHIFT(reg_name, field) reg_name##__##field##__SHIFT
41 #define FD_MASK(reg_name, field) reg_name##__##field##_MASK
47 #define FN(reg_name, field) FD(reg_name##__##field)
58 #define REG_SET_N(reg_name,
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H A Ddmub_dcn315.c43 #define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
H A Ddmub_dcn316.c43 #define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
H A Ddmub_dcn314.c43 #define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
H A Ddmub_dcn351.c14 #define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dce120/
H A Dhw_factory_dce120.c46 #define SF_HPD(reg_name, field_name, post_fix)\
47 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
50 #define SF_HPD(reg_name, field_name, post_fix)\
51 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
60 #define REG(reg_name)\
61 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
63 #define REGI(reg_name, block, id)\
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
65 mm ## block ## id ## _ ## reg_name
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/linux-master/tools/perf/util/
H A Dperf_regs.c35 const char *reg_name = NULL; local
38 reg_name = __perf_reg_name_csky(id);
40 reg_name = __perf_reg_name_loongarch(id);
42 reg_name = __perf_reg_name_mips(id);
44 reg_name = __perf_reg_name_powerpc(id);
46 reg_name = __perf_reg_name_riscv(id);
48 reg_name = __perf_reg_name_s390(id);
50 reg_name = __perf_reg_name_x86(id);
52 reg_name = __perf_reg_name_arm(id);
54 reg_name
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/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
H A Dhw_factory_dcn21.c57 #define REG(reg_name)\
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
60 #define SF_HPD(reg_name, field_name, post_fix)\
61 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
63 #define REGI(reg_name, block, id)\
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
65 mm ## block ## id ## _ ## reg_name
67 #define SF(reg_name, field_name, post_fix)\
68 .field_name = reg_name ## _
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/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
H A Dhw_factory_dcn315.c63 #define REG(reg_name)\
64 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
66 #define SF_HPD(reg_name, field_name, post_fix)\
67 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
69 #define REGI(reg_name, block, id)\
70 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
71 reg ## block ## id ## _ ## reg_name
73 #define SF(reg_name, field_name, post_fix)\
74 .field_name = reg_name ## _
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/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
H A Dhw_factory_dcn20.c59 #define REG(reg_name)\
60 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
62 #define SF_HPD(reg_name, field_name, post_fix)\
63 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
65 #define REGI(reg_name, block, id)\
66 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
67 mm ## block ## id ## _ ## reg_name
69 #define SF(reg_name, field_name, post_fix)\
70 .field_name = reg_name ## _
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/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
H A Dhw_factory_dcn30.c66 #define REG(reg_name)\
67 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
69 #define SF_HPD(reg_name, field_name, post_fix)\
70 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
72 #define REGI(reg_name, block, id)\
73 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
74 mm ## block ## id ## _ ## reg_name
76 #define SF(reg_name, field_name, post_fix)\
77 .field_name = reg_name ## _
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/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
H A Dhw_factory_dcn32.c59 #define REG(reg_name)\
60 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
62 #define SF_HPD(reg_name, field_name, post_fix)\
63 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
65 #define REGI(reg_name, block, id)\
66 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
67 reg ## block ## id ## _ ## reg_name
69 #define SF(reg_name, field_name, post_fix)\
70 .field_name = reg_name ## _
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/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_panel_cntl.h32 #define DCE_PANEL_CNTL_SR(reg_name, block)\
33 .reg_name = mm ## block ## _ ## reg_name
45 #define DCN_PANEL_CNTL_SR(reg_name, block)\
46 .reg_name = BASE(mm ## block ## _ ## reg_name ## _BASE_IDX) + \
47 mm ## block ## _ ## reg_name
59 #define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\
60 .field_name = reg_name ## __ ## field_name ## post_fix
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
H A Dhw_factory_dcn10.c47 #define SF_HPD(reg_name, field_name, post_fix)\
48 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
57 #define REG(reg_name)\
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
60 #define REGI(reg_name, block, id)\
61 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
62 mm ## block ## id ## _ ## reg_name
92 #define SF_DDC(reg_name, field_name, post_fix)\
93 .field_name = reg_name ## _
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/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dce110/
H A Dhw_factory_dce110.c42 #define SF_HPD(reg_name, field_name, post_fix)\
43 .field_name = reg_name ## __ ## field_name ## post_fix
45 #define REG(reg_name)\
46 mm ## reg_name
48 #define REGI(reg_name, block, id)\
49 mm ## block ## id ## _ ## reg_name
79 #define SF_DDC(reg_name, field_name, post_fix)\
80 .field_name = reg_name ## __ ## field_name ## post_fix
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddm_services.h96 #define get_reg_field_value(reg_value, reg_name, reg_field)\
99 reg_name ## __ ## reg_field ## _MASK,\
100 reg_name ## __ ## reg_field ## __SHIFT)
112 #define set_reg_field_value(reg_value, value, reg_name, reg_field)\
116 reg_name ## __ ## reg_field ## _MASK,\
117 reg_name ## __ ## reg_field ## __SHIFT)
157 #define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\
158 generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \
161 #define generic_reg_set_soc15(ctx, inst_offset, reg_name,
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/linux-master/drivers/gpu/drm/amd/display/dc/inc/
H A Dreg_helper.h39 #define REG_READ(reg_name) \
40 dm_read_reg(CTX, REG(reg_name))
42 #define REG_WRITE(reg_name, value) \
43 dm_write_reg(CTX, REG(reg_name), value)
54 #define REG_SET_N(reg_name, n, initial_val, ...) \
56 REG(reg_name), \
60 #define FN(reg_name, field) \
61 FD(reg_name##__##field)
63 #define REG_SET(reg_name, initial_val, field, val) \
64 REG_SET_N(reg_name,
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/linux-master/drivers/media/i2c/ccs/
H A Dccs-reg-access.h36 #define ccs_read(sensor, reg_name, val) \
37 ccs_read_addr(sensor, CCS_R_##reg_name, val)
39 #define ccs_write(sensor, reg_name, val) \
40 ccs_write_addr(sensor, CCS_R_##reg_name, val)
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn301/
H A Ddcn301_hwseq.c39 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr_vbios_smu.c65 #define REG(reg_name) \
66 (MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
68 #define FN(reg_name, field) \
69 FD(reg_name##__##field)
/linux-master/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_opp.h33 #define OPP_SF(reg_name, field_name, post_fix)\
34 .field_name = reg_name ## __ ## field_name ## post_fix
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn303/
H A Ddcn303_hwseq.c42 #define FN(reg_name, field_name) \
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.h34 #define SR(reg_name)\
35 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
36 mm ## reg_name
38 #define SRI(reg_name, block, id)\
39 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
40 mm ## block ## id ## _ ## reg_name
43 #define SRII(reg_name, block, id)\
44 .reg_name[i
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