Searched refs:ref_div (Results 1 - 7 of 7) sorted by relevance

/freebsd-11-stable/sys/mips/atheros/
H A Dar934x_chip.c69 ar934x_get_pll_freq(uint32_t ref, uint32_t ref_div, uint32_t nint, argument
77 t = t / ref_div;
82 t = t / (ref_div * frac);
92 uint32_t pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; local
111 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
118 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
127 cpu_pll = ar934x_get_pll_freq(u_ar71xx_refclk, ref_div, nint,
138 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
145 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
154 ddr_pll = ar934x_get_pll_freq(u_ar71xx_refclk, ref_div, nin
[all...]
H A Dqca953x_chip.c76 uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; local
89 ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
96 cpu_pll = nint * ref_rate / ref_div;
97 cpu_pll += frac * (ref_rate >> 6) / ref_div;
103 ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
110 ddr_pll = nint * ref_rate / ref_div;
111 ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
H A Dqca955x_chip.c77 uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; local
90 ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
97 cpu_pll = nint * ref_rate / ref_div;
98 cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
104 ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
111 ddr_pll = nint * ref_rate / ref_div;
112 ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
/freebsd-11-stable/sys/dev/drm2/radeon/
H A Dradeon_display.c751 u32 ref_div,
755 u32 tmp = post_div * ref_div;
818 u32 ref_div = pll->min_ref_div; local
822 ref_div = pll->reference_div;
825 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
837 while (ref_div <= pll->max_ref_div) {
838 avivo_get_fb_div(pll, target_clock, post_div, ref_div,
843 tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
847 ref_div++;
851 ref_div
748 avivo_get_fb_div(struct radeon_pll *pll, u32 target_clock, u32 post_div, u32 ref_div, u32 *fb_div, u32 *frac_fb_div) argument
939 uint32_t ref_div; local
[all...]
H A Dradeon_clocks.c43 uint32_t fb_div, ref_div, post_div, sclk; local
50 ref_div =
53 if (ref_div == 0)
56 sclk = fb_div / ref_div;
73 uint32_t fb_div, ref_div, post_div, mclk; local
80 ref_div =
83 if (ref_div == 0)
86 mclk = fb_div / ref_div;
356 int ref_div = spll->reference_div; local
358 if (!ref_div)
[all...]
H A Datombios_crtc.c589 /* use recommended ref_div for ss */
775 u32 ref_div,
802 args.v1.usRefDiv = cpu_to_le16(ref_div);
812 args.v2.usRefDiv = cpu_to_le16(ref_div);
822 args.v3.usRefDiv = cpu_to_le16(ref_div);
839 args.v5.ucRefDiv = ref_div;
861 args.v6.ucRefDiv = ref_div;
1000 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; local
1026 &fb_div, &frac_fb_div, &ref_div, &post_div);
1029 &fb_div, &frac_fb_div, &ref_div,
769 atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct radeon_atom_ss *ss) argument
[all...]
H A Dradeon_legacy_crtc.c266 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, argument
271 if (!ref_div)
274 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;

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