/linux-master/drivers/net/ethernet/ibm/emac/ |
H A D | phy.c | 32 #define phy_read _phy_read macro 60 val = phy_read(phy, MII_BMCR); 68 val = phy_read(phy, MII_BMCR); 120 ctl = phy_read(phy, MII_BMCR); 129 adv = phy_read(phy, MII_ADVERTISE); 150 adv = phy_read(phy, MII_CTRL1000); 162 ctl = phy_read(phy, MII_BMCR); 178 ctl = phy_read(phy, MII_BMCR); 211 phy_read(phy, MII_BMSR); 212 status = phy_read(ph [all...] |
/linux-master/drivers/net/phy/ |
H A D | lxt.c | 66 err = phy_read(phydev, MII_BMSR); 71 err = phy_read(phydev, MII_LXT970_ISR); 107 irq_status = phy_read(phydev, MII_BMSR); 113 irq_status = phy_read(phydev, MII_LXT970_ISR); 135 int err = phy_read(phydev, MII_LXT971_ISR); 168 irq_status = phy_read(phydev, MII_LXT971_ISR); 194 status = phy_read(phydev, MII_BMSR); 199 control = phy_read(phydev, MII_BMCR); 205 status = phy_read(phydev, MII_BMSR); 233 adv = phy_read(phyde [all...] |
H A D | uPD60620.c | 40 phy_state = phy_read(phydev, MII_BMSR); 50 phy_state = phy_read(phydev, PHY_PHYSCR); 64 phy_state = phy_read(phydev, MII_LPA);
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H A D | dp83tc811.c | 82 err = phy_read(phydev, MII_DP83811_INT_STAT1); 86 err = phy_read(phydev, MII_DP83811_INT_STAT2); 90 err = phy_read(phydev, MII_DP83811_INT_STAT3); 143 phy_read(phydev, MII_DP83811_INT_STAT1); 204 misr_status = phy_read(phydev, MII_DP83811_INT_STAT1); 221 misr_status = phy_read(phydev, MII_DP83811_INT_STAT2); 236 misr_status = phy_read(phydev, MII_DP83811_INT_STAT3); 277 irq_status = phy_read(phydev, MII_DP83811_INT_STAT1); 285 irq_status = phy_read(phydev, MII_DP83811_INT_STAT2); 293 irq_status = phy_read(phyde [all...] |
H A D | et1011c.c | 49 int ctl = phy_read(phydev, MII_BMCR); 71 val = phy_read(phydev, ET1011C_STATUS_REG); 74 val = phy_read(phydev, ET1011C_CONFIG_REG);
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H A D | amd.c | 36 err = phy_read(phydev, MII_BMSR); 40 err = phy_read(phydev, MII_AM79C_IR); 77 irq_status = phy_read(phydev, MII_AM79C_IR);
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H A D | dp83848.c | 56 int err = phy_read(phydev, DP83848_MISR); 65 control = phy_read(phydev, DP83848_MICR); 98 irq_status = phy_read(phydev, DP83848_MISR); 119 val = phy_read(phydev, MII_BMCR);
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H A D | qsemi.c | 82 err = phy_read(phydev, MII_QS6612_ISR); 87 err = phy_read(phydev, MII_BMSR); 92 err = phy_read(phydev, MII_EXPANSION); 129 irq_status = phy_read(phydev, MII_QS6612_ISR);
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H A D | ste10Xp.c | 35 value = phy_read(phydev, MII_BMCR); 45 value = phy_read(phydev, MII_BMCR); 53 int err = phy_read(phydev, MII_XCIIS); 88 irq_status = phy_read(phydev, MII_XCIIS);
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H A D | ncn26000.c | 76 ret = phy_read(phydev, MII_BMSR); 83 ret = phy_read(phydev, MII_BMSR); 108 ret = phy_read(phydev, NCN26000_REG_IRQ_STATUS); 125 ret = phy_read(phydev, NCN26000_REG_IRQ_STATUS);
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H A D | national.c | 55 return phy_read(phydev, NS_EXP_MEM_DATA); 66 int ret = phy_read(phydev, DP83865_INT_STATUS); 82 irq_status = phy_read(phydev, DP83865_INT_STATUS); 123 int bmcr = phy_read(phydev, MII_BMCR);
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H A D | nxp-cbtx.c | 60 ret = phy_read(phydev, CBTX_MODE_CTRL_STAT); 125 return phy_read(phydev, CBTX_IRQ_STAT); 164 irq_enabled = phy_read(phydev, CBTX_IRQ_ENABLE); 193 ret = phy_read(phydev, CBTX_RX_ERR_COUNTER);
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H A D | bcm63xx.c | 24 reg = phy_read(phydev, MII_BCM63XX_IR); 54 reg = phy_read(phydev, MII_BCM63XX_IR);
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H A D | microchip.c | 41 rc = phy_read(phydev, LAN88XX_INT_STS); 51 rc = phy_read(phydev, LAN88XX_INT_STS); 61 irq_status = phy_read(phydev, LAN88XX_INT_STS); 313 buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL); 356 temp = phy_read(phydev, LAN88XX_INT_MASK); 360 temp = phy_read(phydev, MII_BMCR); 367 temp = phy_read(phydev, LAN88XX_INT_STS); 370 temp = phy_read(phydev, LAN88XX_INT_MASK);
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H A D | nxp-tja11xx.c | 147 ret = phy_read(phydev, MII_ECTRL); 353 ret = phy_read(phydev, MII_INTSRC); 371 ret = phy_read(phydev, MII_CFG1); 381 ret = phy_read(phydev, MII_COMMSTAT); 396 ret = phy_read(phydev, MII_COMMSTAT); 427 ret = phy_read(phydev, tja11xx_hw_stats[i].reg); 445 ret = phy_read(phydev, MII_INTSRC); 454 ret = phy_read(phydev, MII_INTSRC); 636 ret = phy_read(phydev, MII_PHYSID2); 663 ret = phy_read(phyde [all...] |
H A D | davicom.c | 66 int err = phy_read(phydev, MII_DM9161_INTR); 76 temp = phy_read(phydev, MII_DM9161_INTR); 104 irq_status = phy_read(phydev, MII_DM9161_INTR);
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H A D | meson-gxl.c | 81 ret = phy_read(phydev, TSTREAD1); 167 lpa = phy_read(phydev, MII_LPA); 171 exp = phy_read(phydev, MII_EXPANSION);
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H A D | cicada.c | 81 int err = phy_read(phydev, MII_CIS8201_ISTAT); 112 irq_status = phy_read(phydev, MII_CIS8201_ISTAT);
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H A D | rockchip.c | 94 val = phy_read(phydev, MII_INTERNAL_CTRL_STATUS); 126 reg = phy_read(phydev, MII_INTERNAL_CTRL_STATUS);
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H A D | dp83822.c | 191 phy_read(phydev, MII_DP83822_MISR2); 250 misr_status = phy_read(phydev, MII_DP83822_MISR1); 269 misr_status = phy_read(phydev, MII_DP83822_MISR2); 288 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 303 physcr_status = phy_read(phydev, MII_DP83822_PHYSCR); 325 irq_status = phy_read(phydev, MII_DP83822_MISR1); 333 irq_status = phy_read(phydev, MII_DP83822_MISR2); 359 int status = phy_read(phydev, MII_DP83822_PHYSTS); 368 ctrl2 = phy_read(phydev, MII_DP83822_CTRL_2); 468 bmcr = phy_read(phyde [all...] |
H A D | microchip_t1.c | 116 rc = phy_read(phydev, LAN87XX_EXT_REG_CTL); 152 rc = phy_read(phydev, offset); 179 rc = phy_read(phydev, LAN87XX_EXT_REG_RD_DATA); 473 rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE); 504 rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE); 534 irq_status = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE); 562 bmcr = phy_read(phydev, MII_BMCR); 566 bmsr = phy_read(phydev, MII_BMSR); 787 rc = phy_read(phydev, T1_MODE_STAT_REG);
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/linux-master/include/linux/dsa/ |
H A D | lan9303.h | 8 int (*phy_read)(struct lan9303 *chip, int port, int regnum); member in struct:lan9303_phy_ops
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/linux-master/drivers/net/ethernet/realtek/ |
H A D | r8169_firmware.h | 22 rtl_fw_read_t phy_read; member in struct:rtl_fw
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/linux-master/drivers/net/phy/qcom/ |
H A D | qcom-phy-lib.c | 25 return phy_read(phydev, AT803X_DEBUG_DATA); 98 ret = phy_read(phydev, AT803X_INTR_STATUS); 106 irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 126 value = phy_read(phydev, AT803X_INTR_ENABLE); 139 err = phy_read(phydev, AT803X_INTR_STATUS); 150 value = phy_read(phydev, AT803X_INTR_ENABLE); 182 irq_status = phy_read(phydev, AT803X_INTR_STATUS); 189 int_enabled = phy_read(phydev, AT803X_INTR_ENABLE); 214 ss = phy_read(phydev, AT803X_SPECIFIC_STATUS); 221 sfc = phy_read(phyde [all...] |
/linux-master/arch/powerpc/platforms/85xx/ |
H A D | mpc85xx_mds.c | 62 scr = phy_read(phydev, MV88E1111_SCR); 77 scr = phy_read(phydev, MV88E1111_SCR); 98 temp = phy_read(phydev, 30); 114 temp = phy_read(phydev, 30); 119 temp = phy_read(phydev, 30); 132 temp = phy_read(phydev, 16);
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