Searched refs:parents (Results 1 - 25 of 179) sorted by relevance

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/linux-master/drivers/clk/ingenic/
H A Djz4725b-cgu.c56 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
81 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
95 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
104 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
113 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
123 * Disabling MCLK or its parents will render DRAM
127 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
136 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
146 .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
153 .parents
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H A Djz4755-cgu.c53 .parents = { JZ4755_CLK_EXT, },
78 .parents = { JZ4755_CLK_PLL, },
87 .parents = { JZ4755_CLK_EXT, },
96 .parents = { JZ4755_CLK_PLL, },
105 .parents = { JZ4755_CLK_PLL, },
114 .parents = { JZ4755_CLK_PLL, },
123 .parents = { JZ4755_CLK_PLL, },
132 .parents = { JZ4755_CLK_PLL, },
141 .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, },
149 .parents
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H A Djz4770-cgu.c104 .parents = { JZ4770_CLK_EXT },
128 .parents = { JZ4770_CLK_EXT },
157 .parents = { JZ4770_CLK_PLL0, },
165 .parents = { JZ4770_CLK_PLL0, },
173 .parents = { JZ4770_CLK_PLL0, },
182 .parents = { JZ4770_CLK_PLL0, },
190 .parents = { JZ4770_CLK_PLL0, },
199 .parents = { JZ4770_CLK_PLL0, },
210 .parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, },
217 .parents
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H A Djz4760-cgu.c94 .parents = { JZ4760_CLK_EXT },
119 .parents = { JZ4760_CLK_EXT },
149 .parents = { JZ4760_CLK_PLL0, },
157 .parents = { JZ4760_CLK_PLL0, },
165 .parents = { JZ4760_CLK_PLL0, },
173 .parents = { JZ4760_CLK_PLL0, },
182 * Disabling MCLK or its parents will render DRAM
186 .parents = { JZ4760_CLK_PLL0, },
194 .parents = { JZ4760_CLK_PLL0, },
205 .parents
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H A Djz4740-cgu.c71 .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
96 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
110 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
119 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
128 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
138 * Disabling MCLK or its parents will render DRAM
142 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
151 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
161 .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
167 .parents
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H A Dx1830-cgu.c114 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
137 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
160 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
183 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
208 .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
216 .parents = { -1, X1830_CLK_EXCLK, X1830_CLK_APLL, -1 },
222 .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
229 .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
241 .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
247 .parents
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H A Djz4780-cgu.c294 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
300 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
306 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
312 .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
322 .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 },
330 .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK,
337 .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
349 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
360 .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
366 .parents
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H A Dx1000-cgu.c219 .parents = { X1000_CLK_EXCLK },
242 .parents = { X1000_CLK_EXCLK },
267 .parents = { -1, -1, X1000_CLK_EXCLK, -1 },
275 .parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
281 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
292 .parents = { X1000_CLK_CPUMUX },
304 .parents = { X1000_CLK_CPUMUX },
310 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
317 .parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
323 .parents
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/linux-master/drivers/clk/st/
H A Dclkgen-mux.c21 const char **parents; local
28 parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
29 if (!parents)
32 *num_parents = of_clk_parent_fill(np, parents, nparents);
33 return parents;
57 const char **parents; local
76 parents = clkgen_mux_get_parents(np, &num_parents);
77 if (IS_ERR(parents)) {
78 pr_err("%s: Failed to get parents (%ld)\n",
79 __func__, PTR_ERR(parents));
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/linux-master/drivers/clk/starfive/
H A Dclk-starfive-jh71x0.h29 u8 parents[4]; member in struct:jh71x0_clk_data
37 .parents = { [0] = _parent }, \
45 .parents = { [0] = _parent }, \
53 .parents = { [0] = _parent }, \
61 .parents = { [0] = _parent }, \
69 .parents = { __VA_ARGS__ }, \
78 .parents = { __VA_ARGS__ }, \
86 .parents = { __VA_ARGS__ }, \
95 .parents = { __VA_ARGS__ }, \
103 .parents
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H A Dclk-starfive-jh7110-aon.c88 struct clk_parent_data parents[4] = {}; local
92 .parent_data = parents,
101 unsigned int pidx = jh7110_aonclk_data[idx].parents[i];
104 parents[i].hw = &priv->reg[pidx].hw;
106 parents[i].fw_name = "osc";
108 parents[i].fw_name = "gmac0_rmii_refin";
110 parents[i].fw_name = "gmac0_rgmii_rxin";
112 parents[i].fw_name = "stg_axiahb";
114 parents[i].fw_name = "apb_bus";
116 parents[
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H A Dclk-starfive-jh7100-audio.c116 struct clk_parent_data parents[4] = {}; local
120 .parent_data = parents,
128 unsigned int pidx = jh7100_audclk_data[idx].parents[i];
131 parents[i].hw = &priv->reg[pidx].hw;
133 parents[i].fw_name = "audio_src";
135 parents[i].fw_name = "audio_12288";
137 parents[i].fw_name = "dom7ahb_bus";
H A Dclk-starfive-jh7110-stg.c108 struct clk_parent_data parents[4] = {}; local
112 .parent_data = parents,
131 unsigned int pidx = jh7110_stgclk_data[idx].parents[i];
134 parents[i].hw = &priv->reg[pidx].hw;
136 parents[i].fw_name = fw_name[pidx - JH7110_STGCLK_END];
/linux-master/drivers/clk/zynqmp/
H A Dclk-zynqmp.h71 const char * const *parents,
76 const char * const *parents,
82 const char * const *parents,
87 const char * const *parents,
93 const char * const *parents,
H A Dclkc.c25 /* Flags for parents */
68 * @num_parents: Number of parents of clock
99 u32 parents[CLK_GET_PARENTS_RESP_WORDS]; member in struct:parents_resp
123 const char * const *parents,
304 * @parents: Name of this clock's parents
305 * @num_parents: Number of parents
311 const char * const *parents,
335 parents[0],
343 * zynqmp_pm_clock_get_parents() - Get the first 3 parents o
310 zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id, const char * const *parents, u8 num_parents, const struct clock_topology *nodes) argument
476 __zynqmp_clock_get_parents(struct clock_parent *parents, struct parents_resp *response, u32 *nparent) argument
512 zynqmp_clock_get_parents(u32 clk_id, struct clock_parent *parents, u32 *num_parents) argument
551 struct clock_parent *parents; local
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/linux-master/drivers/clk/sunxi/
H A Dclk-sun8i-mbus.c27 const char **parents; local
37 parents = kcalloc(num_parents, sizeof(*parents), GFP_KERNEL);
38 if (!parents)
60 of_clk_parent_fill(node, parents, num_parents);
77 clk = clk_register_composite(NULL, clk_name, parents, num_parents,
89 kfree(parents); /* parents is deep copied */
107 kfree(parents);
H A Dclk-a10-mod1.c26 const char *parents[4]; local
44 i = of_clk_parent_fill(node, parents, SUN4I_MOD1_MAX_PARENTS);
54 clk = clk_register_composite(NULL, clk_name, parents, i,
H A Dclk-a20-gmac.c59 const char *parents[SUN7I_A20_GMAC_PARENTS]; local
74 /* gmac clock requires exactly 2 parents */
75 if (of_clk_parent_fill(node, parents, 2) != 2)
92 parents, SUN7I_A20_GMAC_PARENTS,
H A Dclk-sun4i-display.c19 u8 parents; member in struct:sun4i_a10_display_clk_data
104 const char *parents[4]; local
123 ret = of_clk_parent_fill(node, parents, data->parents);
124 if (ret != data->parents) {
125 pr_err("%s: Could not retrieve the parents\n", clk_name);
158 parents, data->parents,
224 .parents = 4,
242 .parents
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H A Dclk-sun8i-bus-gates.c24 const char *parents[PARENT_MAX]; local
46 parents[i] = of_clk_get_parent_name(node, idx);
82 parents[clk_parent],
/linux-master/fs/xfs/scrub/
H A Dnlinks.h60 xfs_nlink_t parents; member in struct:xchk_nlink
94 uint64_t ret = live->parents;
/linux-master/drivers/gpu/drm/sun4i/
H A Dsun8i_hdmi_phy_clk.c148 const char *parents[2]; local
150 parents[0] = __clk_get_name(phy->clk_pll0);
151 if (!parents[0])
155 parents[1] = __clk_get_name(phy->clk_pll1);
156 if (!parents[1])
166 init.parent_names = parents;
/linux-master/drivers/clk/imx/
H A Dclk-scu.h33 const char * const *parents,
37 const char * const *parents, int num_parents,
57 static inline struct clk_hw *imx_clk_scu2(const char *name, const char * const *parents, argument
60 return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type);
H A Dclk.h148 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \
149 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
151 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \
152 to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
154 #define imx_clk_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \
155 to_clk(imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags))
199 #define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \
200 imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, 0)
202 #define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \
203 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parent
392 __imx_clk_hw_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents, unsigned long flags, unsigned long clk_mux_flags) argument
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/linux-master/drivers/clk/tegra/
H A Dclk-bpmp.c23 unsigned int parents[MRQ_CLK_MAX_PARENTS]; member in struct:tegra_bpmp_clk_info
35 unsigned int *parents; member in struct:tegra_bpmp_clk
208 request.parent_id = clk->parents[index];
249 if (clk->parents[i] == response.parent_id)
374 info->parents[i] = response.parents[i];
415 dev_printk(level, bpmp->dev, " parents: %u\n", info->num_parents);
418 dev_printk(level, bpmp->dev, " %03u\n", info->parents[i]);
450 "clock %u has too many parents (%u, max: %u)\n",
509 const char **parents; local
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