1273929Sjmmv/* SPDX-License-Identifier: GPL-2.0 */ 2240116Smarcel/* 3240116Smarcel * Copyright (C) 2016-2018 Xilinx 4240116Smarcel */ 5240116Smarcel 6240116Smarcel#ifndef __LINUX_CLK_ZYNQMP_H_ 7240116Smarcel#define __LINUX_CLK_ZYNQMP_H_ 8240116Smarcel 9240116Smarcel#include <linux/spinlock.h> 10240116Smarcel 11240116Smarcel#include <linux/firmware/xlnx-zynqmp.h> 12240116Smarcel 13240116Smarcel/* Common Flags */ 14240116Smarcel/* must be gated across rate change */ 15240116Smarcel#define ZYNQMP_CLK_SET_RATE_GATE BIT(0) 16240116Smarcel/* must be gated across re-parent */ 17240116Smarcel#define ZYNQMP_CLK_SET_PARENT_GATE BIT(1) 18240116Smarcel/* propagate rate change up one level */ 19240116Smarcel#define ZYNQMP_CLK_SET_RATE_PARENT BIT(2) 20240116Smarcel/* do not gate even if unused */ 21240116Smarcel#define ZYNQMP_CLK_IGNORE_UNUSED BIT(3) 22240116Smarcel/* don't re-parent on rate change */ 23240116Smarcel#define ZYNQMP_CLK_SET_RATE_NO_REPARENT BIT(7) 24273929Sjmmv/* do not gate, ever */ 25240116Smarcel#define ZYNQMP_CLK_IS_CRITICAL BIT(11) 26273929Sjmmv 27273929Sjmmv/* Type Flags for divider clock */ 28240116Smarcel#define ZYNQMP_CLK_DIVIDER_ONE_BASED BIT(0) 29240116Smarcel#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO BIT(1) 30240116Smarcel#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO BIT(2) 31240116Smarcel#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK BIT(3) 32240116Smarcel#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST BIT(4) 33273929Sjmmv#define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5) 34240116Smarcel#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6) 35240116Smarcel 36240116Smarcel/* Type Flags for mux clock */ 37240116Smarcel#define ZYNQMP_CLK_MUX_INDEX_ONE BIT(0) 38240116Smarcel#define ZYNQMP_CLK_MUX_INDEX_BIT BIT(1) 39240116Smarcel#define ZYNQMP_CLK_MUX_HIWORD_MASK BIT(2) 40240116Smarcel#define ZYNQMP_CLK_MUX_READ_ONLY BIT(3) 41240116Smarcel#define ZYNQMP_CLK_MUX_ROUND_CLOSEST BIT(4) 42240116Smarcel#define ZYNQMP_CLK_MUX_BIG_ENDIAN BIT(5) 43240116Smarcel 44240116Smarcelenum topology_type { 45240116Smarcel TYPE_INVALID, 46240116Smarcel TYPE_MUX, 47240116Smarcel TYPE_PLL, 48240116Smarcel TYPE_FIXEDFACTOR, 49240116Smarcel TYPE_DIV1, 50240116Smarcel TYPE_DIV2, 51240116Smarcel TYPE_GATE, 52240116Smarcel}; 53240116Smarcel 54240116Smarcel/** 55240116Smarcel * struct clock_topology - Clock topology 56240116Smarcel * @type: Type of topology 57240116Smarcel * @flag: Topology flags 58240116Smarcel * @type_flag: Topology type specific flag 59240116Smarcel * @custom_type_flag: Topology type specific custom flag 60240116Smarcel */ 61240116Smarcelstruct clock_topology { 62240116Smarcel u32 type; 63240116Smarcel u32 flag; 64240116Smarcel u32 type_flag; 65240116Smarcel u8 custom_type_flag; 66240116Smarcel}; 67240116Smarcel 68240116Smarcelunsigned long zynqmp_clk_map_common_ccf_flags(const u32 zynqmp_flag); 69240116Smarcel 70240116Smarcelstruct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id, 71240116Smarcel const char * const *parents, 72240116Smarcel u8 num_parents, 73240116Smarcel const struct clock_topology *nodes); 74240116Smarcel 75240116Smarcelstruct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id, 76 const char * const *parents, 77 u8 num_parents, 78 const struct clock_topology *nodes); 79 80struct clk_hw *zynqmp_clk_register_divider(const char *name, 81 u32 clk_id, 82 const char * const *parents, 83 u8 num_parents, 84 const struct clock_topology *nodes); 85 86struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id, 87 const char * const *parents, 88 u8 num_parents, 89 const struct clock_topology *nodes); 90 91struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, 92 u32 clk_id, 93 const char * const *parents, 94 u8 num_parents, 95 const struct clock_topology *nodes); 96 97#endif 98