/linux-master/drivers/gpu/drm/imagination/ |
H A D | pvr_vm_mips.c | 171 start_pfn = (start & fw_dev->fw_heap_info.offset_mask) >> ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K; 172 end_pfn = (end & fw_dev->fw_heap_info.offset_mask) >> ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K; 227 const u32 start_pfn = (start & fw_dev->fw_heap_info.offset_mask) >> 229 const u32 end_pfn = (end & fw_dev->fw_heap_info.offset_mask) >>
|
H A D | pvr_fw.h | 341 /** @offset_mask: Mask for offsets within FW heap. */ 342 u32 offset_mask; member in struct:pvr_fw_device::__anon702
|
H A D | pvr_fw_mips.c | 226 return ((fw_obj->fw_addr_offset + offset) & pvr_dev->fw_dev.fw_heap_info.offset_mask) |
|
H A D | pvr_fw.c | 667 u32 base_addr = private_data->base_addr & pvr_dev->fw_dev.fw_heap_info.offset_mask; 884 fw_dev->fw_heap_info.offset_mask = fw_dev->fw_heap_info.raw_size - 1;
|
/linux-master/drivers/iommu/amd/ |
H A D | io_pgtable_v2.c | 314 unsigned long offset_mask, pte_pgsize; local 321 offset_mask = pte_pgsize - 1; 324 return (__pte & ~offset_mask) | (iova & offset_mask);
|
H A D | io_pgtable.c | 476 unsigned long offset_mask, pte_pgsize; local 484 offset_mask = pte_pgsize - 1; 487 return (__pte & ~offset_mask) | (iova & offset_mask);
|
/linux-master/drivers/soc/mediatek/ |
H A D | mtk-cmdq-helper.c | 196 u16 offset_mask = offset; local 206 offset_mask |= CMDQ_WRITE_ENABLE_MASK; 208 err = cmdq_pkt_write(pkt, subsys, offset_mask, value);
|
/linux-master/drivers/gpu/drm/amd/display/include/ |
H A D | gpio_types.h | 80 uint32_t offset_mask; member in struct:gpio_pin_info
|
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dce110/ |
H A D | hw_translate_dce110.c | 358 info->offset_mask = info->offset - 1;
|
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dce120/ |
H A D | hw_translate_dce120.c | 380 info->offset_mask = info->offset - 1;
|
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dce80/ |
H A D | hw_translate_dce80.c | 392 info->offset_mask = info->offset - 1;
|
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn10/ |
H A D | hw_translate_dcn10.c | 380 info->offset_mask = info->offset - 1;
|
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dce60/ |
H A D | hw_translate_dce60.c | 392 info->offset_mask = info->offset - 1;
|
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn315/ |
H A D | hw_translate_dcn315.c | 344 info->offset_mask = info->offset - 1;
|
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn30/ |
H A D | hw_translate_dcn30.c | 358 info->offset_mask = info->offset - 1;
|
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn32/ |
H A D | hw_translate_dcn32.c | 319 info->offset_mask = info->offset - 1;
|
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn21/ |
H A D | hw_translate_dcn21.c | 356 info->offset_mask = info->offset - 1;
|
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn20/ |
H A D | hw_translate_dcn20.c | 353 info->offset_mask = info->offset - 1;
|
/linux-master/arch/x86/events/amd/ |
H A D | ibs.c | 91 unsigned long offset_mask[1]; member in struct:perf_ibs 678 .offset_mask = { MSR_AMD64_IBSFETCH_REG_MASK }, 703 .offset_mask = { MSR_AMD64_IBSOP_REG_MASK }, 1075 offset = find_next_bit(perf_ibs->offset_mask,
|
/linux-master/drivers/accel/habanalabs/common/mmu/ |
H A D | mmu.c | 480 u64 offset_mask, addr_mask, hop_shift, tmp_phys_addr; local 524 offset_mask = (1ull << hop_shift) - 1; 525 addr_mask = ~(offset_mask); 527 (virt_addr & offset_mask);
|
/linux-master/drivers/mmc/host/ |
H A D | sdhci.c | 1122 unsigned int length_mask, offset_mask; local 1135 offset_mask = 0; 1144 offset_mask = 3; 1150 offset_mask = 3; 1153 if (unlikely(length_mask | offset_mask)) { 1161 if (sg->offset & offset_mask) {
|
/linux-master/drivers/gpu/drm/amd/display/dc/bios/ |
H A D | bios_parser.c | 1824 info->offset_mask = info->offset - 1;
|
H A D | bios_parser2.c | 688 info->offset_mask = info->offset - 1;
|
/linux-master/drivers/net/ethernet/hisilicon/hns3/hns3pf/ |
H A D | hclge_main.c | 6053 u16 data, offset, data_mask, offset_mask; local 6068 offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET; 6082 if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) {
|