/linux-master/drivers/gpu/drm/xe/ |
H A D | xe_gt_ccs_mode.c | 15 static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines) argument 25 xe_assert(xe, num_engines && num_engines <= num_slices); 26 xe_assert(xe, !(num_slices % num_engines)); 46 for (width = num_slices / num_engines; width; width--) { 54 if (hwe->logical_instance >= num_engines) 71 xe_gt_info(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_slices:%d\n", 72 mode, config, num_engines, num_slices); 109 u32 num_engines, num_slices; local 112 ret = kstrtou32(buff, 0, &num_engines); [all...] |
/linux-master/drivers/dma/idxd/ |
H A D | defaults.c | 50 engine->group->num_engines++;
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/linux-master/drivers/gpu/drm/i915/gt/uc/ |
H A D | selftest_guc_multi_lrc.c | 13 static void logical_sort(struct intel_engine_cs **engines, int num_engines) argument 18 for (i = 0; i < num_engines; ++i) 27 sizeof(struct intel_engine_cs *) * num_engines);
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/linux-master/drivers/crypto/intel/qat/qat_common/ |
H A D | adf_hw_arbiter.c | 41 for_each_set_bit(i, &ae_mask, hw_data->num_engines) 98 for (i = 0; i < hw_data->num_engines; i++)
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H A D | adf_heartbeat.c | 54 const size_t max_aes = accel_dev->hw_device->num_engines; 82 const size_t max_aes = accel_dev->hw_device->num_engines; 165 const size_t max_aes = hw_device->num_engines;
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H A D | adf_accel_devices.h | 284 u8 num_engines; member in struct:adf_hw_device_data 315 #define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)
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/linux-master/drivers/crypto/intel/qat/qat_c3xxxvf/ |
H A D | adf_c3xxxvf_hw_data.c | 69 hw_data->num_engines = ADF_C3XXXIOV_MAX_ACCELENGINES;
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/linux-master/drivers/crypto/intel/qat/qat_c62xvf/ |
H A D | adf_c62xvf_hw_data.c | 69 hw_data->num_engines = ADF_C62XIOV_MAX_ACCELENGINES;
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/linux-master/drivers/crypto/intel/qat/qat_dh895xccvf/ |
H A D | adf_dh895xccvf_hw_data.c | 69 hw_data->num_engines = ADF_DH895XCCIOV_MAX_ACCELENGINES;
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/linux-master/drivers/gpu/drm/i915/gem/ |
H A D | i915_gem_context_types.h | 51 /** @num_engines: Number of engines in this set */ 52 unsigned int num_engines; member in struct:i915_gem_engines
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H A D | i915_gem_context.c | 394 unsigned num_engines; member in struct:set_proto_ctx_engines 417 if (idx >= set->num_engines) { 419 idx, set->num_engines); 423 idx = array_index_nospec(idx, set->num_engines); 508 if (idx >= set->num_engines) { 511 idx, set->num_engines); 515 idx = array_index_nospec(idx, set->num_engines); 609 if (slot >= set->num_engines) { 611 slot, set->num_engines); 758 set.num_engines 1186 user_engines(struct i915_gem_context *ctx, unsigned int num_engines, struct i915_gem_proto_engine *pe) argument [all...] |
H A D | i915_gem_context.h | 214 else if (likely(idx < e->num_engines && e->engines[idx]))
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/linux-master/drivers/gpu/drm/omapdrm/ |
H A D | omap_dmm_priv.h | 168 int num_engines; member in struct:dmm
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H A D | omap_dmm_tiler.c | 283 for (i = 0; i < dmm->num_engines; i++) { 754 REFILL_BUFFER_SIZE * omap_dmm->num_engines, 836 omap_dmm->num_engines = (hwinfo >> 24) & 0x1F; 841 atomic_set(&omap_dmm->engine_counter, omap_dmm->num_engines); 877 REFILL_BUFFER_SIZE * omap_dmm->num_engines, 886 omap_dmm->engines = kcalloc(omap_dmm->num_engines, 893 for (i = 0; i < omap_dmm->num_engines; i++) {
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/linux-master/drivers/gpu/drm/i915/gt/ |
H A D | intel_gt_types.h | 258 u8 num_engines; member in struct:intel_gt::intel_gt_info
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H A D | intel_ring_submission.c | 695 const int num_engines = local 696 IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0; 703 len += 2 + (num_engines ? 4 * num_engines + 6 : 0); 720 if (num_engines) { 723 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); 773 if (num_engines) { 777 *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
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H A D | intel_engine.h | 296 unsigned int num_engines, 300 return engines[0]->cops->create_parallel(engines, num_engines, width); 295 intel_engine_create_parallel(struct intel_engine_cs **engines, unsigned int num_engines, unsigned int width) argument
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/linux-master/drivers/crypto/intel/qat/qat_c62x/ |
H A D | adf_c62x_hw_data.c | 125 hw_data->num_engines = ADF_C62X_MAX_ACCELENGINES;
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/linux-master/drivers/crypto/intel/qat/qat_c3xxx/ |
H A D | adf_c3xxx_hw_data.c | 123 hw_data->num_engines = ADF_C3XXX_MAX_ACCELENGINES;
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/linux-master/drivers/gpu/drm/i915/gem/selftests/ |
H A D | mock_context.c | 136 engines->num_engines = 1;
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H A D | i915_gem_context.c | 318 count = engines->num_engines; 1369 unsigned long idx, ndwords, dw, num_engines; local 1409 num_engines = 0; 1412 num_engines++; 1461 ndwords, num_engines); 1775 unsigned long num_engines, count; local 1841 num_engines = 0; 1883 num_engines++; 1886 count, num_engines);
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/linux-master/drivers/gpu/drm/i915/ |
H A D | i915_perf_types.h | 420 * @num_engines: The number of engines using this OA unit. 422 u32 num_engines; member in struct:i915_perf_group
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/linux-master/drivers/infiniband/hw/hfi1/ |
H A D | sdma.c | 1248 * @num_engines: num sdma engines 1253 void sdma_clean(struct hfi1_devdata *dd, size_t num_engines) argument 1272 for (i = 0; dd->per_sdma && i < num_engines; ++i) { 1329 size_t num_engines = chip_sdma_engines(dd); local 1341 num_engines = mod_num_sdma; 1349 chip_sdma_mem_size(dd) / (num_engines * SDMA_BLOCK_SIZE); 1357 num_engines, descq_cnt); 1360 dd->per_sdma = kcalloc_node(num_engines, sizeof(*dd->per_sdma), 1377 for (this_idx = 0; this_idx < num_engines; ++this_idx) { 1443 dd->sdma_heads_size = L1_CACHE_BYTES * num_engines; [all...] |
/linux-master/drivers/crypto/intel/qat/qat_dh895xcc/ |
H A D | adf_dh895xcc_hw_data.c | 219 hw_data->num_engines = ADF_DH895XCC_MAX_ACCELENGINES;
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/linux-master/include/uapi/drm/ |
H A D | xe_drm.h | 263 /** @num_engines: number of engines returned in @engines */ 264 __u32 num_engines; member in struct:drm_xe_query_engines 649 * for (int i = 0; i < engines->num_engines; i++) {
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