/linux-master/drivers/clk/mstar/ |
H A D | clk-msc313-mpll.c | 47 struct msc313_mpll *mpll = to_mpll(hw); local 51 regmap_field_read(mpll->input_div, &input_div); 52 regmap_field_read(mpll->output_div, &output_div); 53 regmap_field_read(mpll->loop_div_first, &loop_first); 54 regmap_field_read(mpll->loop_div_second, &loop_second); 74 struct msc313_mpll *mpll; local 82 mpll = devm_kzalloc(dev, sizeof(*mpll), GFP_KERNEL); 83 if (!mpll) 94 mpll [all...] |
H A D | Makefile | 7 obj-$(CONFIG_MSTAR_MSC313_MPLL) += clk-msc313-mpll.o
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/linux-master/drivers/clk/meson/ |
H A D | clk-mpll.c | 19 #include "clk-mpll.h" 79 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); local 83 sdm = meson_parm_read(clk->map, &mpll->sdm); 84 n2 = meson_parm_read(clk->map, &mpll->n2); 93 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); local 98 mpll->flags); 113 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); local 117 params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags); 119 if (mpll->lock) 120 spin_lock_irqsave(mpll 141 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); local [all...] |
H A D | Makefile | 9 obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o
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/linux-master/drivers/gpu/drm/radeon/ |
H A D | radeon_clocks.c | 72 struct radeon_pll *mpll = &rdev->clock.mpll; local 78 fb_div *= mpll->reference_freq; 112 struct radeon_pll *mpll = &rdev->clock.mpll; local 150 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; 151 spll->reference_div = mpll->reference_div = 187 struct radeon_pll *mpll = &rdev->clock.mpll; local 219 if (mpll [all...] |
H A D | radeon_combios.c | 737 struct radeon_pll *mpll = &rdev->clock.mpll; local 778 mpll->reference_freq = RBIOS16(pll_info + 0x26); 779 mpll->reference_div = RBIOS16(pll_info + 0x28); 780 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); 781 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); 784 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); 785 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); 788 mpll->pll_in_min = 40; 789 mpll [all...] |
H A D | radeon_atombios.c | 1136 struct radeon_pll *mpll = &rdev->clock.mpll; local 1215 mpll->reference_freq = 1218 mpll->reference_freq = 1220 mpll->reference_div = 0; 1222 mpll->pll_out_min = 1224 mpll->pll_out_max = 1228 if (mpll->pll_out_min == 0) { 1230 mpll->pll_out_min = 64800; 1232 mpll [all...] |
H A D | rv740_dpm.c | 250 u32 reference_clock = rdev->clock.mpll.reference_freq;
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H A D | rv730_dpm.c | 169 u32 reference_clock = rdev->clock.mpll.reference_freq;
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H A D | cypress_dpm.c | 442 u32 ref_clk = rdev->clock.mpll.reference_freq; 558 u32 reference_clock = rdev->clock.mpll.reference_freq;
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H A D | rv6xx_dpm.c | 655 u32 ref_clk = rdev->clock.mpll.reference_freq;
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/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
H A D | nv04.c | 288 bool mpll = Preg == 0x4020; local 291 uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) | 306 if (mpll) { 322 Pval |= mpll ? 1 << 12 : 1 << 8; 326 if (mpll) { 340 if (mpll) { 349 if (mpll) {
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/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_atomfirmware.c | 660 struct amdgpu_pll *mpll = &adev->clock.mpll; local 719 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz); 721 mpll->reference_div = 0; 722 mpll->min_post_div = 1; 723 mpll->max_post_div = 1; 724 mpll->min_ref_div = 2; 725 mpll->max_ref_div = 0xff; 726 mpll->min_feedback_div = 4; 727 mpll [all...] |
H A D | amdgpu_atombios.c | 571 struct amdgpu_pll *mpll = &adev->clock.mpll; local 643 mpll->reference_freq = 645 mpll->reference_div = 0; 647 mpll->pll_out_min = 649 mpll->pll_out_max = 653 if (mpll->pll_out_min == 0) 654 mpll->pll_out_min = 64800; 656 mpll->pll_in_min = 658 mpll [all...] |
H A D | amdgpu.h | 404 struct amdgpu_pll mpll; member in struct:amdgpu_clock
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/linux-master/drivers/phy/qualcomm/ |
H A D | phy-qcom-ipq806x-usb.c | 62 /* Override value for mpll */ 125 u32 mpll; member in struct:usb_phy 406 data |= SSPHY_MPLL(phy_dwc3->mpll); 532 if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll)) 533 phy_dwc3->mpll = SSPHY_MPLL_VALUE;
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/linux-master/drivers/clk/imx/ |
H A D | clk-imx31.c | 33 static const char *mcu_main_sel[] = { "spll", "mpll", }; 39 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator in enum:mx31_clks 58 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL);
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H A D | clk-imx35.c | 64 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, enumerator in enum:mx35_clks 108 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); 111 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); 116 clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm);
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H A D | clk-imx25.c | 46 static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", }; 54 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator in enum:mx25_clks 82 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); 84 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
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/linux-master/drivers/clk/samsung/ |
H A D | clk-exynos5410.c | 64 apll, cpll, epll, mpll, enumerator in enum:exynos5410_plls 249 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
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H A D | clk-s5pv210.c | 69 mpll, enumerator in enum:__anon160 718 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll", 730 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
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H A D | clk-exynos4.c | 150 apll, mpll, epll, vpll, enumerator in enum:exynos4_plls 1153 [mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 1164 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
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H A D | clk-exynos5250.c | 108 apll, mpll, cpll, epll, vpll, gpll, bpll, enumerator in enum:exynos5250_plls 738 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
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H A D | clk-exynos5420.c | 153 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, enumerator in enum:exynos5x_plls 1481 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
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/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
H A D | ramnv50.c | 225 struct nvbios_pll mpll; local 327 ret = nvbios_pll_parse(bios, 0x004008, &mpll); 328 mpll.vco2.max_freq = 0; 330 ret = nv04_pll_calc(subdev, &mpll, freq, 348 r004008 |= (mpll.bias_p << 19) | (P << 22) | (P << 16);
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