History log of /linux-master/drivers/clk/mstar/clk-msc313-mpll.c
Revision Date Author Comments
# d90afa62 15-Feb-2021 Daniel Palmer <daniel@0x0f.com>

clk: mstar: msc313-mpll: Fix format specifier

The output dividers are unsigned int so the format specifier
should have been %u not %d.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Link: https://lore.kernel.org/r/20210215115710.3762276-2-daniel@0x0f.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>


# bef7a78d 10-Feb-2021 Daniel Palmer <daniel@0x0f.com>

clk: mstar: MStar/SigmaStar MPLL driver

This adds a basic driver for the MPLL block found in MStar/SigmaStar
ARMv7 SoCs.

Currently this driver is only good for calculating the rates of it's
outputs and the actual configuration must be done before the kernel
boots. Usually this is done even before u-boot starts.

This driver targets the MPLL block found in the MSC313/MSC313E but
there is no documentation this chip so the register descriptions for
the another MStar chip the MST786 were used as they seem to match.

Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Link: https://lore.kernel.org/r/20210211052206.2955988-5-daniel@0x0f.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>