Searched refs:mpcc (Results 1 - 13 of 13) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_mpc.c62 static void mpc201_init_mpcc(struct mpcc *mpcc, int mpcc_inst) argument
64 mpcc->mpcc_id = mpcc_inst;
65 mpcc->dpp_id = 0xf;
66 mpcc->mpcc_bot = NULL;
67 mpcc->blnd_cfg.overlap_only = false;
68 mpcc->blnd_cfg.global_alpha = 0xff;
69 mpcc->blnd_cfg.global_gain = 0xff;
70 mpcc->blnd_cfg.background_color_bpc = 4;
71 mpcc
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/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dmpc.h198 * struct mpcc - MPCC connection and blending configuration for a single MPCC instance.
202 struct mpcc { struct
216 struct mpcc *mpcc_bot;
250 struct mpcc *opp_list;
257 struct mpcc mpcc_array[MAX_MPCC];
310 * struct mpcc* - MPCC that was added.
312 struct mpcc* (*insert_plane)(
317 struct mpcc *insert_above_mpcc,
330 * - [in/out] mpcc - MPCC to be removed from tree.
339 struct mpcc *mpc
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H A Dopp.h217 int mpcc[MAX_PIPES]; member in struct:mpc_tree_cfg
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_mpc.c45 struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id);
50 /* find bottommost mpcc. */
82 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); local
91 mpcc->blnd_cfg = *blnd_cfg;
119 struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id)
127 struct mpcc *mpc1_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)
129 struct mpcc *tmp_mpcc = tree->opp_list;
193 * Return: struct mpcc* - MPCC that was added.
195 struct mpcc *mpc1_insert_plan
352 mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst) argument
421 struct mpcc *mpcc; local
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H A Ddcn10_mpc.h141 struct mpcc *mpc1_insert_plane(
146 struct mpcc *insert_above_mpcc,
153 struct mpcc *mpcc);
188 struct mpcc *mpc1_get_mpcc(
192 struct mpcc *mpc1_get_mpcc_for_dpp(
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.c55 struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); local
70 mpcc->blnd_cfg = *blnd_cfg;
511 static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst) argument
513 mpcc->mpcc_id = mpcc_inst;
514 mpcc->dpp_id = 0xf;
515 mpcc->mpcc_bot = NULL;
516 mpcc->blnd_cfg.overlap_only = false;
517 mpcc
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mpc.c1032 void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst) argument
1034 mpcc->mpcc_id = mpcc_inst;
1035 mpcc->dpp_id = 0xf;
1036 mpcc->mpcc_bot = NULL;
1037 mpcc->blnd_cfg.overlap_only = false;
1038 mpcc->blnd_cfg.global_alpha = 0xff;
1039 mpcc->blnd_cfg.global_gain = 0xff;
1040 mpcc->blnd_cfg.background_color_bpc = 4;
1041 mpcc
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H A Ddcn30_mpc.h1092 void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c381 struct mpcc *mpcc_to_remove = NULL;
426 struct mpcc *new_mpcc;
427 struct mpcc *remove_mpcc = NULL;
475 * we do mpcc_remove but the mpcc cannot go to idle
/linux-master/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h369 uint32_t mpcc : 1; member in struct:pipe_update_flags::__anon231
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c1512 new_pipe->update_flags.bits.mpcc = 1;
1572 * Assume mpcc inst = pipe index, if not this code needs to be updated
1573 * since mpcc is what is affected by these. In fact all of our sequence
1575 * same index mpcc reset.
1583 * Detect mpcc blending changes, only dpp inst and opp matter here,
1589 new_pipe->update_flags.bits.mpcc = 1;
1732 if (pipe_ctx->update_flags.bits.mpcc
2071 /* Disconnect mpcc */
2087 DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
2101 * Program all updated pipes, order matters for mpcc setu
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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c1373 phantom_pipe->update_flags.bits.mpcc = 1;
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c1244 struct mpcc *mpcc_to_remove = NULL;
1418 /* num_opp will be equal to number of mpcc */
2676 struct mpcc *new_mpcc;
2710 * we do mpcc_remove but the mpcc cannot go to idle

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