/linux-master/drivers/thermal/ |
H A D | thermal_mmio.c | 12 void __iomem *mmio_base; member in struct:thermal_mmio 13 u32 (*read_mmio)(void __iomem *mmio_base); 18 static u32 thermal_mmio_readb(void __iomem *mmio_base) argument 20 return readb(mmio_base); 28 t = sensor->read_mmio(sensor->mmio_base) & sensor->mask; 53 sensor->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 54 if (IS_ERR(sensor->mmio_base)) 55 return PTR_ERR(sensor->mmio_base);
|
/linux-master/drivers/input/keyboard/ |
H A D | imx_keypad.c | 49 void __iomem *mmio_base; member in struct:imx_keypad 94 reg_val = readw(keypad->mmio_base + KPDR); 96 writew(reg_val, keypad->mmio_base + KPDR); 98 reg_val = readw(keypad->mmio_base + KPCR); 100 writew(reg_val, keypad->mmio_base + KPCR); 104 reg_val = readw(keypad->mmio_base + KPCR); 106 writew(reg_val, keypad->mmio_base + KPCR); 113 reg_val = readw(keypad->mmio_base + KPDR); 115 writew(reg_val, keypad->mmio_base + KPDR); 127 reg_val = readw(keypad->mmio_base [all...] |
/linux-master/drivers/edac/ |
H A D | al_mc_edac.c | 57 void __iomem *mmio_base; member in struct:al_mc_edac 83 eccerrcnt = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_ERR_COUNT); 88 ecccaddr0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_ADDR0); 89 ecccaddr1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_ADDR1); 90 ecccsyn0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND0); 91 ecccsyn1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND1); 92 ecccsyn2 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND2); 95 al_mc->mmio_base + AL_MC_ECC_CLEAR); 128 eccerrcnt = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_ERR_COUNT); 133 eccuaddr0 = readl_relaxed(al_mc->mmio_base 195 get_scrub_mode(void __iomem *mmio_base) argument 222 void __iomem *mmio_base; local [all...] |
/linux-master/drivers/pwm/ |
H A D | pwm-tiecap.c | 36 void __iomem *mmio_base; member in struct:ecap_pwm_chip 74 value = readw(pc->mmio_base + ECCTL2); 79 writew(value, pc->mmio_base + ECCTL2); 83 writel(duty_cycles, pc->mmio_base + CAP2); 84 writel(period_cycles, pc->mmio_base + CAP1); 91 writel(duty_cycles, pc->mmio_base + CAP4); 92 writel(period_cycles, pc->mmio_base + CAP3); 96 value = readw(pc->mmio_base + ECCTL2); 99 writew(value, pc->mmio_base + ECCTL2); 115 value = readw(pc->mmio_base [all...] |
H A D | pwm-imx1.c | 30 void __iomem *mmio_base; member in struct:pwm_imx1_chip 87 max = readl(imx->mmio_base + MX1_PWMP); 90 writel(max - p, imx->mmio_base + MX1_PWMS); 105 value = readl(imx->mmio_base + MX1_PWMC); 107 writel(value, imx->mmio_base + MX1_PWMC); 117 value = readl(imx->mmio_base + MX1_PWMC); 119 writel(value, imx->mmio_base + MX1_PWMC); 181 imx->mmio_base = devm_platform_ioremap_resource(pdev, 0); 182 if (IS_ERR(imx->mmio_base)) 183 return PTR_ERR(imx->mmio_base); [all...] |
H A D | pwm-tiehrpwm.c | 109 void __iomem *mmio_base; member in struct:ehrpwm_pwm_chip 210 ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val); 277 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval); 284 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW); 286 ehrpwm_write(pc->mmio_base, TBPRD, period_cycles); 289 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK, 299 ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles); 337 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, 340 ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); 371 ehrpwm_modify(pc->mmio_base, AQSFR [all...] |
H A D | pwm-imx27.c | 85 void __iomem *mmio_base; member in struct:pwm_imx27_chip 135 val = readl(imx->mmio_base + MX3_PWMCR); 155 val = readl(imx->mmio_base + MX3_PWMPR); 167 val = readl(imx->mmio_base + MX3_PWMSAR); 186 writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR); 189 cr = readl(imx->mmio_base + MX3_PWMCR); 206 sr = readl(imx->mmio_base + MX3_PWMSR); 213 sr = readl(imx->mmio_base + MX3_PWMSR); 266 writel(duty_cycles, imx->mmio_base + MX3_PWMSAR); 267 writel(period_cycles, imx->mmio_base [all...] |
H A D | pwm-pxa.c | 55 void __iomem *mmio_base; member in struct:pxa_pwm_chip 95 writel(prescale | PWMCR_SD, pc->mmio_base + offset + PWMCR); 96 writel(dc, pc->mmio_base + offset + PWMDCR); 97 writel(pv, pc->mmio_base + offset + PWMPCR); 187 pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); 188 if (IS_ERR(pc->mmio_base)) 189 return PTR_ERR(pc->mmio_base);
|
H A D | pwm-spear.c | 49 * @mmio_base: base address of pwm chip 53 void __iomem *mmio_base; member in struct:spear_pwm_chip 65 return readl_relaxed(chip->mmio_base + (num << 4) + offset); 72 writel_relaxed(val, chip->mmio_base + (num << 4) + offset); 205 pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); 206 if (IS_ERR(pc->mmio_base)) 207 return PTR_ERR(pc->mmio_base); 226 val = readl_relaxed(pc->mmio_base + PWMMCR); 228 writel_relaxed(val, pc->mmio_base + PWMMCR);
|
/linux-master/drivers/net/wireless/broadcom/b43/ |
H A D | pio.h | 72 u16 mmio_base; member in struct:b43_pio_txqueue 101 u16 mmio_base; member in struct:b43_pio_rxqueue 111 return b43_read16(q->dev, q->mmio_base + offset); 116 return b43_read32(q->dev, q->mmio_base + offset); 122 b43_write16(q->dev, q->mmio_base + offset, value); 128 b43_write32(q->dev, q->mmio_base + offset, value); 134 return b43_read16(q->dev, q->mmio_base + offset); 139 return b43_read32(q->dev, q->mmio_base + offset); 145 b43_write16(q->dev, q->mmio_base + offset, value); 151 b43_write32(q->dev, q->mmio_base [all...] |
/linux-master/drivers/clk/mmp/ |
H A D | clk-audio.c | 61 void __iomem *mmio_base; member in struct:mmp2_audio_clk 125 aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0); 133 aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1); 216 writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL0); 220 writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL1); 257 priv->sspa_mux.reg = priv->mmio_base + SSPA_AUD_CTRL; 267 priv->sysclk_div.reg = priv->mmio_base + SSPA_AUD_CTRL; 280 priv->sysclk_gate.reg = priv->mmio_base + SSPA_AUD_CTRL; 288 priv->sspa0_div.reg = priv->mmio_base + SSPA_AUD_CTRL; 301 priv->sspa0_gate.reg = priv->mmio_base [all...] |
/linux-master/drivers/thermal/intel/int340x_thermal/ |
H A D | processor_thermal_power_floor.c | 42 status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET); 94 int_status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET); 117 status = readq(proc_priv->mmio_base + SOC_WT_RES_INT_STATUS_OFFSET);
|
H A D | processor_thermal_mbox.c | 29 data = readl(proc_priv->mmio_base + MBOX_OFFSET_INTERFACE); 52 writel(data, (proc_priv->mmio_base + MBOX_OFFSET_DATA)); 55 writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE)); 73 writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE)); 80 *resp = readl(proc_priv->mmio_base + MBOX_OFFSET_DATA); 82 *resp = readq(proc_priv->mmio_base + MBOX_OFFSET_DATA);
|
/linux-master/drivers/usb/host/ |
H A D | ohci-pxa27x.c | 120 void __iomem *mmio_base; member in struct:pxa27x_ohci 139 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA); 140 uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB); 164 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA); 165 __raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB); 220 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); 221 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA); 253 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); 254 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA); 259 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base [all...] |
/linux-master/drivers/ata/ |
H A D | sata_sil.c | 254 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; local 255 void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2; 280 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; local 281 void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2; 348 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; local 349 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode; 509 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; local 517 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2); 538 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; local 542 writel(0, mmio_base 566 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; local 653 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; local 727 void __iomem *mmio_base; local [all...] |
H A D | pata_pdc2027x.c | 461 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; local 467 bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff; 468 bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; 471 bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff; 472 bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; 502 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; local 521 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); 560 iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL); 561 ioread16(mmio_base + PDC_PLL_CTL); /* flush */ 570 pll_ctl = ioread16(mmio_base 585 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; local 690 void __iomem *mmio_base; local [all...] |
H A D | sata_qstor.c | 192 u8 __iomem *mmio_base = qs_mmio_base(ap->host); local 194 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */ 200 u8 __iomem *mmio_base = qs_mmio_base(ap->host); local 203 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */ 354 u8 __iomem *mmio_base = qs_mmio_base(host); local 357 u32 sff0 = readl(mmio_base + QS_HST_SFF); 358 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4); 460 void __iomem *mmio_base = qs_mmio_base(ap->host); local 461 void __iomem *chan = mmio_base + (ap->port_no * 0x4000); 482 void __iomem *mmio_base local 490 void __iomem *mmio_base = host->iomap[QS_MMIO_BAR]; local 528 qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base) argument [all...] |
H A D | pata_sil680.c | 340 void __iomem *mmio_base; local 380 mmio_base = host->iomap[SIL680_MMIO_BAR]; 381 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00; 382 host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80; 383 host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a; 384 host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a; 386 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08; 387 host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0; 388 host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca; 389 host->ports[1]->ioaddr.altstatus_addr = mmio_base [all...] |
/linux-master/drivers/rtc/ |
H A D | rtc-ep93xx.c | 30 void __iomem *mmio_base; member in struct:ep93xx_rtc 40 comp = readl(ep93xx_rtc->mmio_base + EP93XX_RTC_SWCOMP); 58 time = readl(ep93xx_rtc->mmio_base + EP93XX_RTC_DATA); 69 writel(secs + 1, ep93xx_rtc->mmio_base + EP93XX_RTC_LOAD); 132 ep93xx_rtc->mmio_base = devm_platform_ioremap_resource(pdev, 0); 133 if (IS_ERR(ep93xx_rtc->mmio_base)) 134 return PTR_ERR(ep93xx_rtc->mmio_base);
|
/linux-master/drivers/net/wireless/broadcom/b43legacy/ |
H A D | pio.h | 53 u16 mmio_base; member in struct:b43legacy_pioqueue 87 return b43legacy_read16(queue->dev, queue->mmio_base + offset); 94 b43legacy_write16(queue->dev, queue->mmio_base + offset, value);
|
/linux-master/drivers/ufs/host/ |
H A D | tc-dwc-g210-pci.c | 60 void __iomem *mmio_base; local 89 mmio_base = pcim_iomap_table(pdev)[0]; 99 err = ufshcd_init(hba, mmio_base, pdev->irq);
|
/linux-master/drivers/gpu/drm/xe/ |
H A D | xe_hw_engine.c | 40 u32 mmio_base; member in struct:engine_info 50 .mmio_base = RENDER_RING_BASE, 58 .mmio_base = BLT_RING_BASE, 66 .mmio_base = XEHPC_BCS1_RING_BASE, 74 .mmio_base = XEHPC_BCS2_RING_BASE, 82 .mmio_base = XEHPC_BCS3_RING_BASE, 90 .mmio_base = XEHPC_BCS4_RING_BASE, 98 .mmio_base = XEHPC_BCS5_RING_BASE, 106 .mmio_base = XEHPC_BCS6_RING_BASE, 114 .mmio_base [all...] |
H A D | xe_rtp.c | 114 u32 mmio_base, 124 sr_entry.reg.addr += mmio_base; 133 u32 mmio_base; local 142 mmio_base = hwe->mmio_base; 144 mmio_base = 0; 146 rtp_add_sr_entry(action, gt, mmio_base, sr); 216 * entries with matching rules to @sr. If @hwe is not NULL, its mmio_base is 112 rtp_add_sr_entry(const struct xe_rtp_action *action, struct xe_gt *gt, u32 mmio_base, struct xe_reg_sr *sr) argument
|
/linux-master/drivers/misc/vmw_vmci/ |
H A D | vmci_guest.c | 55 void __iomem *mmio_base; member in struct:vmci_guest_device 104 if (dev->mmio_base != NULL) 105 return readl(dev->mmio_base + reg); 111 if (dev->mmio_base != NULL) 112 writel(val, dev->mmio_base + reg); 120 if (vmci_dev->mmio_base == NULL) 152 if (dev->mmio_base != NULL) { 312 bool is_io_port = vmci_dev->mmio_base == NULL; 555 if (vmci_dev->mmio_base != NULL) { 579 void __iomem *mmio_base local [all...] |
/linux-master/drivers/soundwire/ |
H A D | intel_init.c | 65 link->mmio_base = res->mmio_base; 67 link->registers = res->mmio_base + SDW_LINK_BASE 70 link->shim = res->mmio_base + res->shim_base; 71 link->alh = res->mmio_base + res->alh_base; 74 link->registers = res->mmio_base + SDW_IP_BASE(link_id); 76 link->shim = res->mmio_base + SDW_SHIM2_GENERIC_BASE(link_id); 77 link->shim_vs = res->mmio_base + SDW_SHIM2_VS_BASE(link_id); 205 ctx->mmio_base = res->mmio_base; [all...] |