| /linux-master/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_4_2_d.h | 71 #define mmUVD_RBC_RB_RPTR 0x3da4 macro
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| H A D | uvd_4_0_d.h | 71 #define mmUVD_RBC_RB_RPTR 0x3DA4 macro
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| H A D | uvd_3_1_d.h | 73 #define mmUVD_RBC_RB_RPTR 0x3da4 macro
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| H A D | uvd_6_0_d.h | 93 #define mmUVD_RBC_RB_RPTR 0x3da4 macro
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| H A D | uvd_5_0_d.h | 77 #define mmUVD_RBC_RB_RPTR 0x3da4 macro
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| H A D | uvd_7_0_offset.h | 198 #define mmUVD_RBC_RB_RPTR 0x05a4 macro
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| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | uvd_v5_0.c | 60 return RREG32(mmUVD_RBC_RB_RPTR);
444 WREG32(mmUVD_RBC_RB_RPTR, 0);
446 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
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| H A D | uvd_v4_2.c | 62 return RREG32(mmUVD_RBC_RB_RPTR);
387 WREG32(mmUVD_RBC_RB_RPTR, 0x0);
389 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
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| H A D | uvd_v3_1.c | 48 return RREG32(mmUVD_RBC_RB_RPTR);
424 WREG32(mmUVD_RBC_RB_RPTR, 0x0);
426 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
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| H A D | vcn_v1_0.c | 933 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
937 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1091 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1095 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1186 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1386 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
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| H A D | vcn_v2_0.c | 915 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
919 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1075 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1077 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1121 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1328 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
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| H A D | vcn_v3_0.c | 1075 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0);
1079 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);
1252 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
1255 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
1514 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1660 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr);
1693 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);
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| H A D | vcn_v2_5.c | 950 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0);
954 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);
1130 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
1132 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
1371 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1537 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);
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| H A D | uvd_v6_0.c | 81 return RREG32(mmUVD_RBC_RB_RPTR);
859 WREG32(mmUVD_RBC_RB_RPTR, 0);
861 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
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| H A D | uvd_v7_0.c | 75 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
1107 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0);
1109 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);
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| /linux-master/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 384 #define mmUVD_RBC_RB_RPTR 0x05a4 macro
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| H A D | vcn_2_0_0_offset.h | 680 #define mmUVD_RBC_RB_RPTR 0x0264 macro
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| H A D | vcn_2_5_offset.h | 789 #define mmUVD_RBC_RB_RPTR 0x02e0 macro
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| H A D | vcn_3_0_0_offset.h | 1173 #define mmUVD_RBC_RB_RPTR 0x02e0 macro
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