Searched refs:mmSDMA1_RLC2_RB_WPTR_POLL_CNTL (Results 1 - 6 of 6) sorted by last modified time
| /linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 1549 #define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL 0x0807 macro
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| H A D | gc_10_3_0_offset.h | 1600 #define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL 0x07e7 macro
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| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v5_0.c | 85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
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| H A D | sdma_v4_0.c | 201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
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| /linux-master/drivers/gpu/drm/amd/include/asic_reg/sdma1/ |
| H A D | sdma1_4_2_2_offset.h | 552 #define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL 0x01e7 macro
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| H A D | sdma1_4_2_offset.h | 548 #define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL 0x0207 macro
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