Searched refs:mmSDMA0_RLC4_RB_WPTR_POLL_CNTL (Results 1 - 6 of 6) sorted by last modified time
| /linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 716 #define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL 0x02c7 macro
[all...] |
| H A D | gc_10_3_0_offset.h | 734 #define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL 0x0297 macro
[all...] |
| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v5_0.c | 75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
|
| H A D | sdma_v4_0.c | 175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
|
| /linux-master/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_2_2_offset.h | 728 #define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL 0x0297 macro
|
| H A D | sdma0_4_2_offset.h | 724 #define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL 0x02c7 macro
|
Completed in 796 milliseconds