Searched refs:mmSDMA0_GFX_RB_BASE (Results 1 - 16 of 16) sorted by last modified time

/linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h204 #define mmSDMA0_GFX_RB_BASE 0x0081 macro
[all...]
H A Dgc_10_3_0_offset.h192 #define mmSDMA0_GFX_RB_BASE 0x0081 macro
[all...]
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_2.c530 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
H A Dsdma_v5_0.c723 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
H A Dsdma_v4_0.c1069 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
H A Dsdma_v3_0.c689 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
H A Dsdma_v2_4.c448 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
H A Dcik_sdma.c474 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
/linux-master/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_2_2_offset.h210 #define mmSDMA0_GFX_RB_BASE 0x0081 macro
H A Dsdma0_4_2_offset.h206 #define mmSDMA0_GFX_RB_BASE 0x0081 macro
H A Dsdma0_4_1_offset.h206 #define mmSDMA0_GFX_RB_BASE 0x0081 macro
H A Dsdma0_4_0_offset.h210 #define mmSDMA0_GFX_RB_BASE 0x0081 macro
/linux-master/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_d.h247 #define mmSDMA0_GFX_RB_BASE 0x3481 macro
H A Doss_2_4_d.h188 #define mmSDMA0_GFX_RB_BASE 0x3481 macro
H A Doss_3_0_1_d.h215 #define mmSDMA0_GFX_RB_BASE 0x3481 macro
H A Doss_3_0_d.h340 #define mmSDMA0_GFX_RB_BASE 0x3481 macro

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