Searched refs:mmSDMA0_CNTL (Results 1 - 16 of 16) sorted by last modified time

/linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h45 #define mmSDMA0_CNTL 0x001c macro
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H A Dgc_10_3_0_offset.h52 #define mmSDMA0_CNTL 0x001c macro
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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_2.c429 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
432 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
570 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
575 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
1383 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
H A Dsdma_v5_0.c611 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
625 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
766 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
771 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
1531 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1532 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
H A Dsdma_v4_0.c964 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
972 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
1211 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1215 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1218 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1221 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1236 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1239 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1367 temp = RREG32_SDMA(i, mmSDMA0_CNTL);
1369 WREG32_SDMA(i, mmSDMA0_CNTL, tem
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H A Dsdma_v3_0.c576 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
595 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
1334 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1336 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1339 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1341 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1350 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1352 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1355 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1357 WREG32(mmSDMA0_CNTL
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H A Dsdma_v2_4.c998 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1000 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1003 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1005 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1014 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1016 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1019 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1021 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
H A Dcik_sdma.c369 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
384 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
1107 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1109 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1112 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1114 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1123 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1125 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1128 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1130 WREG32(mmSDMA0_CNTL
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_2_2_offset.h70 #define mmSDMA0_CNTL 0x001c macro
H A Dsdma0_4_2_offset.h70 #define mmSDMA0_CNTL 0x001c macro
H A Dsdma0_4_1_offset.h68 #define mmSDMA0_CNTL 0x001c macro
H A Dsdma0_4_0_offset.h70 #define mmSDMA0_CNTL 0x001c macro
/linux-master/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_d.h223 #define mmSDMA0_CNTL 0x3404 macro
H A Doss_2_4_d.h161 #define mmSDMA0_CNTL 0x3404 macro
H A Doss_3_0_1_d.h158 #define mmSDMA0_CNTL 0x3404 macro
H A Doss_3_0_d.h295 #define mmSDMA0_CNTL 0x3404 macro

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