Searched refs:mmMP1_SMN_C2PMSG_66 (Results 1 - 15 of 15) sorted by relevance

/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu9_smumgr.c101 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
H A Dsmu10_smumgr.c67 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
H A Dvega20_smumgr.c94 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
/linux-master/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_9_0_offset.h262 #define mmMP1_SMN_C2PMSG_66 0x0282 macro
H A Dmp_10_0_offset.h250 #define mmMP1_SMN_C2PMSG_66 0x0282 macro
H A Dmp_12_0_0_offset.h250 #define mmMP1_SMN_C2PMSG_66 0x0282 macro
H A Dmp_11_0_8_offset.h250 #define mmMP1_SMN_C2PMSG_66 0x0282 macro
H A Dmp_11_0_offset.h252 #define mmMP1_SMN_C2PMSG_66 0x0282 macro
H A Dmp_11_5_0_offset.h250 #define mmMP1_SMN_C2PMSG_66 0x0282 macro
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_4_ppt.c46 #define mmMP1_SMN_C2PMSG_66 0x0282 macro
1142 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
H A Dsmu_v13_0.c64 #define mmMP1_SMN_C2PMSG_66 0x0282 macro
2438 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
H A Dsmu_v13_0_0_ppt.c73 #define mmMP1_SMN_C2PMSG_66 0x0282 macro
2857 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c44 #define mmMP1_SMN_C2PMSG_66 0x0282 macro
1480 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0_0_ppt.c46 #define mmMP1_SMN_C2PMSG_66 0x0282 macro
1458 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c2200 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);

Completed in 313 milliseconds