| /linux-master/sound/hda/ |
| H A D | intel-nhlt.c | 176 int mclk_mask = 0; local
223 mclk_mask |= blob[mdivc_offset] & GENMASK(1, 0);
232 if (hweight_long(mclk_mask) != 1)
235 return mclk_mask;
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| /linux-master/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| H A D | renoir_ppt.c | 253 uint32_t *mclk_mask,
261 if (mclk_mask)
263 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
269 if (mclk_mask)
271 *mclk_mask = 0;
286 uint32_t mclk_mask, soc_mask; local
320 &mclk_mask,
337 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
935 uint32_t sclk_mask, mclk_mask, soc_mask; local
1017 &mclk_mask,
250 renoir_get_profiling_clk_mask(struct smu_context *smu, enum amd_dpm_forced_level level, uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) argument
[all...] |
| /linux-master/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | vangogh_ppt.c | 805 uint32_t *mclk_mask,
812 if (mclk_mask)
813 *mclk_mask = clk_table->NumDfPstatesEnabled - 1;
821 if (mclk_mask)
822 *mclk_mask = 0;
836 if (mclk_mask)
837 *mclk_mask = 0;
896 uint32_t mclk_mask; local
940 &mclk_mask,
949 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, ma
801 vangogh_get_profiling_clk_mask(struct smu_context *smu, enum amd_dpm_forced_level level, uint32_t *vclk_mask, uint32_t *dclk_mask, uint32_t *mclk_mask, uint32_t *fclk_mask, uint32_t *soc_mask) argument
1380 uint32_t soc_mask, mclk_mask, fclk_mask; local
[all...] |
| /linux-master/sound/soc/sof/intel/ |
| H A D | hda.c | 1736 int mclk_mask; local
1762 mclk_mask = check_nhlt_ssp_mclk_mask(sdev, ssp_num);
1764 if (mclk_mask < 0) {
1769 dev_dbg(sdev->dev, "MCLK mask %#x found in NHLT\n", mclk_mask);
1771 if (mclk_mask) {
1772 dev_info(sdev->dev, "Overriding topology with MCLK mask %#x from NHLT\n", mclk_mask);
1774 sdev->mclk_id_quirk = (mclk_mask & BIT(0)) ? 0 : 1;
|
| /linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega12_hwmgr.c | 1718 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
1726 *mclk_mask = 0;
1733 *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL;
1740 *mclk_mask = 0;
1743 *mclk_mask = mem_dpm_table->count - 1;
1773 uint32_t mclk_mask = 0; local
1790 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
1794 vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
1717 vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) argument
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| H A D | vega20_hwmgr.c | 2523 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
2531 *mclk_mask = 0;
2538 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL;
2545 *mclk_mask = 0;
2548 *mclk_mask = mem_dpm_table->count - 1;
2723 uint32_t sclk_mask, mclk_mask, soc_mask; local
2742 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
2746 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
2522 vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) argument
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| H A D | vega10_hwmgr.c | 4183 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
4193 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL;
4199 *mclk_mask = 0;
4209 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1;
4301 uint32_t mclk_mask = 0; local
4318 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4322 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
4182 vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) argument
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| H A D | smu7_hwmgr.c | 3170 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask)
3188 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
3191 *mclk_mask = golden_dpm_table->mclk_table.count - 2;
3227 *mclk_mask = 0;
3229 *mclk_mask = golden_dpm_table->mclk_table.count - 1;
3241 uint32_t mclk_mask = 0; local
3258 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
3262 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
3169 smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) argument
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