1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2// 3// This file is provided under a dual BSD/GPLv2 license. When using or 4// redistributing this file, you may do so under either license. 5// 6// Copyright(c) 2018 Intel Corporation. All rights reserved. 7// 8// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com> 9// Ranjani Sridharan <ranjani.sridharan@linux.intel.com> 10// Rander Wang <rander.wang@intel.com> 11// Keyon Jie <yang.jie@linux.intel.com> 12// 13 14/* 15 * Hardware interface for generic Intel audio DSP HDA IP 16 */ 17 18#include <sound/hdaudio_ext.h> 19#include <sound/hda_register.h> 20 21#include <linux/acpi.h> 22#include <linux/module.h> 23#include <linux/soundwire/sdw.h> 24#include <linux/soundwire/sdw_intel.h> 25#include <sound/intel-dsp-config.h> 26#include <sound/intel-nhlt.h> 27#include <sound/sof.h> 28#include <sound/sof/xtensa.h> 29#include <sound/hda-mlink.h> 30#include "../sof-audio.h" 31#include "../sof-pci-dev.h" 32#include "../ops.h" 33#include "hda.h" 34#include "telemetry.h" 35 36#define CREATE_TRACE_POINTS 37#include <trace/events/sof_intel.h> 38 39#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) 40#include <sound/soc-acpi-intel-match.h> 41#endif 42 43/* platform specific devices */ 44#include "shim.h" 45 46#define EXCEPT_MAX_HDR_SIZE 0x400 47#define HDA_EXT_ROM_STATUS_SIZE 8 48 49static void hda_get_interfaces(struct snd_sof_dev *sdev, u32 *interface_mask) 50{ 51 const struct sof_intel_dsp_desc *chip; 52 53 chip = get_chip_info(sdev->pdata); 54 switch (chip->hw_ip_version) { 55 case SOF_INTEL_TANGIER: 56 case SOF_INTEL_BAYTRAIL: 57 case SOF_INTEL_BROADWELL: 58 interface_mask[SOF_DAI_DSP_ACCESS] = BIT(SOF_DAI_INTEL_SSP); 59 break; 60 case SOF_INTEL_CAVS_1_5: 61 case SOF_INTEL_CAVS_1_5_PLUS: 62 interface_mask[SOF_DAI_DSP_ACCESS] = 63 BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | BIT(SOF_DAI_INTEL_HDA); 64 interface_mask[SOF_DAI_HOST_ACCESS] = BIT(SOF_DAI_INTEL_HDA); 65 break; 66 case SOF_INTEL_CAVS_1_8: 67 case SOF_INTEL_CAVS_2_0: 68 case SOF_INTEL_CAVS_2_5: 69 case SOF_INTEL_ACE_1_0: 70 interface_mask[SOF_DAI_DSP_ACCESS] = 71 BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | 72 BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH); 73 interface_mask[SOF_DAI_HOST_ACCESS] = BIT(SOF_DAI_INTEL_HDA); 74 break; 75 case SOF_INTEL_ACE_2_0: 76 interface_mask[SOF_DAI_DSP_ACCESS] = 77 BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) | 78 BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH); 79 /* all interfaces accessible without DSP */ 80 interface_mask[SOF_DAI_HOST_ACCESS] = 81 interface_mask[SOF_DAI_DSP_ACCESS]; 82 break; 83 default: 84 break; 85 } 86} 87 88static u32 hda_get_interface_mask(struct snd_sof_dev *sdev) 89{ 90 u32 interface_mask[SOF_DAI_ACCESS_NUM] = { 0 }; 91 92 hda_get_interfaces(sdev, interface_mask); 93 94 return interface_mask[sdev->dspless_mode_selected]; 95} 96 97bool hda_is_chain_dma_supported(struct snd_sof_dev *sdev, u32 dai_type) 98{ 99 u32 interface_mask[SOF_DAI_ACCESS_NUM] = { 0 }; 100 const struct sof_intel_dsp_desc *chip; 101 102 if (sdev->dspless_mode_selected) 103 return false; 104 105 hda_get_interfaces(sdev, interface_mask); 106 107 if (!(interface_mask[SOF_DAI_DSP_ACCESS] & BIT(dai_type))) 108 return false; 109 110 if (dai_type == SOF_DAI_INTEL_HDA) 111 return true; 112 113 switch (dai_type) { 114 case SOF_DAI_INTEL_SSP: 115 case SOF_DAI_INTEL_DMIC: 116 case SOF_DAI_INTEL_ALH: 117 chip = get_chip_info(sdev->pdata); 118 if (chip->hw_ip_version < SOF_INTEL_ACE_2_0) 119 return false; 120 return true; 121 default: 122 return false; 123 } 124} 125 126#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 127 128/* 129 * The default for SoundWire clock stop quirks is to power gate the IP 130 * and do a Bus Reset, this will need to be modified when the DSP 131 * needs to remain in D0i3 so that the Master does not lose context 132 * and enumeration is not required on clock restart 133 */ 134static int sdw_clock_stop_quirks = SDW_INTEL_CLK_STOP_BUS_RESET; 135module_param(sdw_clock_stop_quirks, int, 0444); 136MODULE_PARM_DESC(sdw_clock_stop_quirks, "SOF SoundWire clock stop quirks"); 137 138static int sdw_params_stream(struct device *dev, 139 struct sdw_intel_stream_params_data *params_data) 140{ 141 struct snd_soc_dai *d = params_data->dai; 142 struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(d, params_data->substream->stream); 143 struct snd_sof_dai_config_data data = { 0 }; 144 145 data.dai_index = (params_data->link_id << 8) | d->id; 146 data.dai_data = params_data->alh_stream_id; 147 148 return hda_dai_config(w, SOF_DAI_CONFIG_FLAGS_HW_PARAMS, &data); 149} 150 151struct sdw_intel_ops sdw_callback = { 152 .params_stream = sdw_params_stream, 153}; 154 155static int sdw_ace2x_params_stream(struct device *dev, 156 struct sdw_intel_stream_params_data *params_data) 157{ 158 return sdw_hda_dai_hw_params(params_data->substream, 159 params_data->hw_params, 160 params_data->dai, 161 params_data->link_id); 162} 163 164static int sdw_ace2x_free_stream(struct device *dev, 165 struct sdw_intel_stream_free_data *free_data) 166{ 167 return sdw_hda_dai_hw_free(free_data->substream, 168 free_data->dai, 169 free_data->link_id); 170} 171 172static int sdw_ace2x_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) 173{ 174 return sdw_hda_dai_trigger(substream, cmd, dai); 175} 176 177static struct sdw_intel_ops sdw_ace2x_callback = { 178 .params_stream = sdw_ace2x_params_stream, 179 .free_stream = sdw_ace2x_free_stream, 180 .trigger = sdw_ace2x_trigger, 181}; 182 183void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable) 184{ 185 struct sof_intel_hda_dev *hdev; 186 187 hdev = sdev->pdata->hw_pdata; 188 189 if (!hdev->sdw) 190 return; 191 192 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC2, 193 HDA_DSP_REG_ADSPIC2_SNDW, 194 enable ? HDA_DSP_REG_ADSPIC2_SNDW : 0); 195} 196 197void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable) 198{ 199 u32 interface_mask = hda_get_interface_mask(sdev); 200 const struct sof_intel_dsp_desc *chip; 201 202 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 203 return; 204 205 chip = get_chip_info(sdev->pdata); 206 if (chip && chip->enable_sdw_irq) 207 chip->enable_sdw_irq(sdev, enable); 208} 209 210static int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 211{ 212 u32 interface_mask = hda_get_interface_mask(sdev); 213 struct sof_intel_hda_dev *hdev; 214 acpi_handle handle; 215 int ret; 216 217 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 218 return -EINVAL; 219 220 handle = ACPI_HANDLE(sdev->dev); 221 222 /* save ACPI info for the probe step */ 223 hdev = sdev->pdata->hw_pdata; 224 225 ret = sdw_intel_acpi_scan(handle, &hdev->info); 226 if (ret < 0) 227 return -EINVAL; 228 229 return 0; 230} 231 232static int hda_sdw_probe(struct snd_sof_dev *sdev) 233{ 234 const struct sof_intel_dsp_desc *chip; 235 struct sof_intel_hda_dev *hdev; 236 struct sdw_intel_res res; 237 void *sdw; 238 239 hdev = sdev->pdata->hw_pdata; 240 241 memset(&res, 0, sizeof(res)); 242 243 chip = get_chip_info(sdev->pdata); 244 if (chip->hw_ip_version < SOF_INTEL_ACE_2_0) { 245 res.mmio_base = sdev->bar[HDA_DSP_BAR]; 246 res.hw_ops = &sdw_intel_cnl_hw_ops; 247 res.shim_base = hdev->desc->sdw_shim_base; 248 res.alh_base = hdev->desc->sdw_alh_base; 249 res.ext = false; 250 res.ops = &sdw_callback; 251 } else { 252 /* 253 * retrieve eml_lock needed to protect shared registers 254 * in the HDaudio multi-link areas 255 */ 256 res.eml_lock = hdac_bus_eml_get_mutex(sof_to_bus(sdev), true, 257 AZX_REG_ML_LEPTR_ID_SDW); 258 if (!res.eml_lock) 259 return -ENODEV; 260 261 res.mmio_base = sdev->bar[HDA_DSP_HDA_BAR]; 262 /* 263 * the SHIM and SoundWire register offsets are link-specific 264 * and will be determined when adding auxiliary devices 265 */ 266 res.hw_ops = &sdw_intel_lnl_hw_ops; 267 res.ext = true; 268 res.ops = &sdw_ace2x_callback; 269 270 } 271 res.irq = sdev->ipc_irq; 272 res.handle = hdev->info.handle; 273 res.parent = sdev->dev; 274 275 res.dev = sdev->dev; 276 res.clock_stop_quirks = sdw_clock_stop_quirks; 277 res.hbus = sof_to_bus(sdev); 278 279 /* 280 * ops and arg fields are not populated for now, 281 * they will be needed when the DAI callbacks are 282 * provided 283 */ 284 285 /* we could filter links here if needed, e.g for quirks */ 286 res.count = hdev->info.count; 287 res.link_mask = hdev->info.link_mask; 288 289 sdw = sdw_intel_probe(&res); 290 if (!sdw) { 291 dev_err(sdev->dev, "error: SoundWire probe failed\n"); 292 return -EINVAL; 293 } 294 295 /* save context */ 296 hdev->sdw = sdw; 297 298 return 0; 299} 300 301int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev) 302{ 303 struct sof_intel_hda_dev *hdev; 304 struct sdw_intel_ctx *ctx; 305 u32 caps; 306 307 hdev = sdev->pdata->hw_pdata; 308 ctx = hdev->sdw; 309 310 caps = snd_sof_dsp_read(sdev, HDA_DSP_BAR, ctx->shim_base + SDW_SHIM_LCAP); 311 caps &= SDW_SHIM_LCAP_LCOUNT_MASK; 312 313 /* Check HW supported vs property value */ 314 if (caps < ctx->count) { 315 dev_err(sdev->dev, 316 "%s: BIOS master count %d is larger than hardware capabilities %d\n", 317 __func__, ctx->count, caps); 318 return -EINVAL; 319 } 320 321 return 0; 322} 323 324int hda_sdw_check_lcount_ext(struct snd_sof_dev *sdev) 325{ 326 struct sof_intel_hda_dev *hdev; 327 struct sdw_intel_ctx *ctx; 328 struct hdac_bus *bus; 329 u32 slcount; 330 331 bus = sof_to_bus(sdev); 332 333 hdev = sdev->pdata->hw_pdata; 334 ctx = hdev->sdw; 335 336 slcount = hdac_bus_eml_get_count(bus, true, AZX_REG_ML_LEPTR_ID_SDW); 337 338 /* Check HW supported vs property value */ 339 if (slcount < ctx->count) { 340 dev_err(sdev->dev, 341 "%s: BIOS master count %d is larger than hardware capabilities %d\n", 342 __func__, ctx->count, slcount); 343 return -EINVAL; 344 } 345 346 return 0; 347} 348 349static int hda_sdw_check_lcount(struct snd_sof_dev *sdev) 350{ 351 const struct sof_intel_dsp_desc *chip; 352 353 chip = get_chip_info(sdev->pdata); 354 if (chip && chip->read_sdw_lcount) 355 return chip->read_sdw_lcount(sdev); 356 357 return 0; 358} 359 360int hda_sdw_startup(struct snd_sof_dev *sdev) 361{ 362 struct sof_intel_hda_dev *hdev; 363 struct snd_sof_pdata *pdata = sdev->pdata; 364 int ret; 365 366 hdev = sdev->pdata->hw_pdata; 367 368 if (!hdev->sdw) 369 return 0; 370 371 if (pdata->machine && !pdata->machine->mach_params.link_mask) 372 return 0; 373 374 ret = hda_sdw_check_lcount(sdev); 375 if (ret < 0) 376 return ret; 377 378 return sdw_intel_startup(hdev->sdw); 379} 380 381static int hda_sdw_exit(struct snd_sof_dev *sdev) 382{ 383 struct sof_intel_hda_dev *hdev; 384 385 hdev = sdev->pdata->hw_pdata; 386 387 hda_sdw_int_enable(sdev, false); 388 389 if (hdev->sdw) 390 sdw_intel_exit(hdev->sdw); 391 hdev->sdw = NULL; 392 393 return 0; 394} 395 396bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev) 397{ 398 struct sof_intel_hda_dev *hdev; 399 bool ret = false; 400 u32 irq_status; 401 402 hdev = sdev->pdata->hw_pdata; 403 404 if (!hdev->sdw) 405 return ret; 406 407 /* store status */ 408 irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS2); 409 410 /* invalid message ? */ 411 if (irq_status == 0xffffffff) 412 goto out; 413 414 /* SDW message ? */ 415 if (irq_status & HDA_DSP_REG_ADSPIS2_SNDW) 416 ret = true; 417 418out: 419 return ret; 420} 421 422static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 423{ 424 u32 interface_mask = hda_get_interface_mask(sdev); 425 const struct sof_intel_dsp_desc *chip; 426 427 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 428 return false; 429 430 chip = get_chip_info(sdev->pdata); 431 if (chip && chip->check_sdw_irq) 432 return chip->check_sdw_irq(sdev); 433 434 return false; 435} 436 437static irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 438{ 439 return sdw_intel_thread(irq, context); 440} 441 442bool hda_sdw_check_wakeen_irq_common(struct snd_sof_dev *sdev) 443{ 444 struct sof_intel_hda_dev *hdev; 445 446 hdev = sdev->pdata->hw_pdata; 447 if (hdev->sdw && 448 snd_sof_dsp_read(sdev, HDA_DSP_BAR, 449 hdev->desc->sdw_shim_base + SDW_SHIM_WAKESTS)) 450 return true; 451 452 return false; 453} 454 455static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 456{ 457 u32 interface_mask = hda_get_interface_mask(sdev); 458 const struct sof_intel_dsp_desc *chip; 459 460 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 461 return false; 462 463 chip = get_chip_info(sdev->pdata); 464 if (chip && chip->check_sdw_wakeen_irq) 465 return chip->check_sdw_wakeen_irq(sdev); 466 467 return false; 468} 469 470void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) 471{ 472 u32 interface_mask = hda_get_interface_mask(sdev); 473 struct sof_intel_hda_dev *hdev; 474 475 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 476 return; 477 478 hdev = sdev->pdata->hw_pdata; 479 if (!hdev->sdw) 480 return; 481 482 sdw_intel_process_wakeen_event(hdev->sdw); 483} 484 485#else /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */ 486static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev) 487{ 488 return 0; 489} 490 491static inline int hda_sdw_probe(struct snd_sof_dev *sdev) 492{ 493 return 0; 494} 495 496static inline int hda_sdw_exit(struct snd_sof_dev *sdev) 497{ 498 return 0; 499} 500 501static inline bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) 502{ 503 return false; 504} 505 506static inline irqreturn_t hda_dsp_sdw_thread(int irq, void *context) 507{ 508 return IRQ_HANDLED; 509} 510 511static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) 512{ 513 return false; 514} 515 516#endif /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */ 517 518/* 519 * Debug 520 */ 521 522struct hda_dsp_msg_code { 523 u32 code; 524 const char *text; 525}; 526 527#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG) 528static bool hda_use_msi = true; 529module_param_named(use_msi, hda_use_msi, bool, 0444); 530MODULE_PARM_DESC(use_msi, "SOF HDA use PCI MSI mode"); 531#else 532#define hda_use_msi (1) 533#endif 534 535int sof_hda_position_quirk = SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS; 536module_param_named(position_quirk, sof_hda_position_quirk, int, 0444); 537MODULE_PARM_DESC(position_quirk, "SOF HDaudio position quirk"); 538 539static char *hda_model; 540module_param(hda_model, charp, 0444); 541MODULE_PARM_DESC(hda_model, "Use the given HDA board model."); 542 543static int dmic_num_override = -1; 544module_param_named(dmic_num, dmic_num_override, int, 0444); 545MODULE_PARM_DESC(dmic_num, "SOF HDA DMIC number"); 546 547static int mclk_id_override = -1; 548module_param_named(mclk_id, mclk_id_override, int, 0444); 549MODULE_PARM_DESC(mclk_id, "SOF SSP mclk_id"); 550 551static const struct hda_dsp_msg_code hda_dsp_rom_fw_error_texts[] = { 552 {HDA_DSP_ROM_CSE_ERROR, "error: cse error"}, 553 {HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"}, 554 {HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"}, 555 {HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"}, 556 {HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"}, 557 {HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"}, 558 {HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"}, 559 {HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"}, 560 {HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"}, 561 {HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"}, 562 {HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"}, 563 {HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"}, 564 {HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"}, 565 {HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"}, 566 {HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"}, 567 {HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"}, 568}; 569 570#define FSR_ROM_STATE_ENTRY(state) {FSR_STATE_ROM_##state, #state} 571static const struct hda_dsp_msg_code fsr_rom_state_names[] = { 572 FSR_ROM_STATE_ENTRY(INIT), 573 FSR_ROM_STATE_ENTRY(INIT_DONE), 574 FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED), 575 FSR_ROM_STATE_ENTRY(FW_MANIFEST_LOADED), 576 FSR_ROM_STATE_ENTRY(FW_FW_LOADED), 577 FSR_ROM_STATE_ENTRY(FW_ENTERED), 578 FSR_ROM_STATE_ENTRY(VERIFY_FEATURE_MASK), 579 FSR_ROM_STATE_ENTRY(GET_LOAD_OFFSET), 580 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT), 581 FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT_DONE), 582 /* CSE states */ 583 FSR_ROM_STATE_ENTRY(CSE_IMR_REQUEST), 584 FSR_ROM_STATE_ENTRY(CSE_IMR_GRANTED), 585 FSR_ROM_STATE_ENTRY(CSE_VALIDATE_IMAGE_REQUEST), 586 FSR_ROM_STATE_ENTRY(CSE_IMAGE_VALIDATED), 587 FSR_ROM_STATE_ENTRY(CSE_IPC_IFACE_INIT), 588 FSR_ROM_STATE_ENTRY(CSE_IPC_RESET_PHASE_1), 589 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL_ENTRY), 590 FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL), 591 FSR_ROM_STATE_ENTRY(CSE_IPC_DOWN), 592}; 593 594#define FSR_BRINGUP_STATE_ENTRY(state) {FSR_STATE_BRINGUP_##state, #state} 595static const struct hda_dsp_msg_code fsr_bringup_state_names[] = { 596 FSR_BRINGUP_STATE_ENTRY(INIT), 597 FSR_BRINGUP_STATE_ENTRY(INIT_DONE), 598 FSR_BRINGUP_STATE_ENTRY(HPSRAM_LOAD), 599 FSR_BRINGUP_STATE_ENTRY(UNPACK_START), 600 FSR_BRINGUP_STATE_ENTRY(IMR_RESTORE), 601 FSR_BRINGUP_STATE_ENTRY(FW_ENTERED), 602}; 603 604#define FSR_WAIT_STATE_ENTRY(state) {FSR_WAIT_FOR_##state, #state} 605static const struct hda_dsp_msg_code fsr_wait_state_names[] = { 606 FSR_WAIT_STATE_ENTRY(IPC_BUSY), 607 FSR_WAIT_STATE_ENTRY(IPC_DONE), 608 FSR_WAIT_STATE_ENTRY(CACHE_INVALIDATION), 609 FSR_WAIT_STATE_ENTRY(LP_SRAM_OFF), 610 FSR_WAIT_STATE_ENTRY(DMA_BUFFER_FULL), 611 FSR_WAIT_STATE_ENTRY(CSE_CSR), 612}; 613 614#define FSR_MODULE_NAME_ENTRY(mod) [FSR_MOD_##mod] = #mod 615static const char * const fsr_module_names[] = { 616 FSR_MODULE_NAME_ENTRY(ROM), 617 FSR_MODULE_NAME_ENTRY(ROM_BYP), 618 FSR_MODULE_NAME_ENTRY(BASE_FW), 619 FSR_MODULE_NAME_ENTRY(LP_BOOT), 620 FSR_MODULE_NAME_ENTRY(BRNGUP), 621 FSR_MODULE_NAME_ENTRY(ROM_EXT), 622}; 623 624static const char * 625hda_dsp_get_state_text(u32 code, const struct hda_dsp_msg_code *msg_code, 626 size_t array_size) 627{ 628 int i; 629 630 for (i = 0; i < array_size; i++) { 631 if (code == msg_code[i].code) 632 return msg_code[i].text; 633 } 634 635 return NULL; 636} 637 638static void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level) 639{ 640 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 641 const char *state_text, *error_text, *module_text; 642 u32 fsr, state, wait_state, module, error_code; 643 644 fsr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg); 645 state = FSR_TO_STATE_CODE(fsr); 646 wait_state = FSR_TO_WAIT_STATE_CODE(fsr); 647 module = FSR_TO_MODULE_CODE(fsr); 648 649 if (module > FSR_MOD_ROM_EXT) 650 module_text = "unknown"; 651 else 652 module_text = fsr_module_names[module]; 653 654 if (module == FSR_MOD_BRNGUP) 655 state_text = hda_dsp_get_state_text(state, fsr_bringup_state_names, 656 ARRAY_SIZE(fsr_bringup_state_names)); 657 else 658 state_text = hda_dsp_get_state_text(state, fsr_rom_state_names, 659 ARRAY_SIZE(fsr_rom_state_names)); 660 661 /* not for us, must be generic sof message */ 662 if (!state_text) { 663 dev_printk(level, sdev->dev, "%#010x: unknown ROM status value\n", fsr); 664 return; 665 } 666 667 if (wait_state) { 668 const char *wait_state_text; 669 670 wait_state_text = hda_dsp_get_state_text(wait_state, fsr_wait_state_names, 671 ARRAY_SIZE(fsr_wait_state_names)); 672 if (!wait_state_text) 673 wait_state_text = "unknown"; 674 675 dev_printk(level, sdev->dev, 676 "%#010x: module: %s, state: %s, waiting for: %s, %s\n", 677 fsr, module_text, state_text, wait_state_text, 678 fsr & FSR_HALTED ? "not running" : "running"); 679 } else { 680 dev_printk(level, sdev->dev, "%#010x: module: %s, state: %s, %s\n", 681 fsr, module_text, state_text, 682 fsr & FSR_HALTED ? "not running" : "running"); 683 } 684 685 error_code = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + 4); 686 if (!error_code) 687 return; 688 689 error_text = hda_dsp_get_state_text(error_code, hda_dsp_rom_fw_error_texts, 690 ARRAY_SIZE(hda_dsp_rom_fw_error_texts)); 691 if (!error_text) 692 error_text = "unknown"; 693 694 if (state == FSR_STATE_FW_ENTERED) 695 dev_printk(level, sdev->dev, "status code: %#x (%s)\n", error_code, 696 error_text); 697 else 698 dev_printk(level, sdev->dev, "error code: %#x (%s)\n", error_code, 699 error_text); 700} 701 702static void hda_dsp_get_registers(struct snd_sof_dev *sdev, 703 struct sof_ipc_dsp_oops_xtensa *xoops, 704 struct sof_ipc_panic_info *panic_info, 705 u32 *stack, size_t stack_words) 706{ 707 u32 offset = sdev->dsp_oops_offset; 708 709 /* first read registers */ 710 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops)); 711 712 /* note: variable AR register array is not read */ 713 714 /* then get panic info */ 715 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) { 716 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n", 717 xoops->arch_hdr.totalsize); 718 return; 719 } 720 offset += xoops->arch_hdr.totalsize; 721 sof_block_read(sdev, sdev->mmio_bar, offset, 722 panic_info, sizeof(*panic_info)); 723 724 /* then get the stack */ 725 offset += sizeof(*panic_info); 726 sof_block_read(sdev, sdev->mmio_bar, offset, stack, 727 stack_words * sizeof(u32)); 728} 729 730/* dump the first 8 dwords representing the extended ROM status */ 731static void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level, 732 u32 flags) 733{ 734 const struct sof_intel_dsp_desc *chip; 735 char msg[128]; 736 int len = 0; 737 u32 value; 738 int i; 739 740 chip = get_chip_info(sdev->pdata); 741 for (i = 0; i < HDA_EXT_ROM_STATUS_SIZE; i++) { 742 value = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + i * 0x4); 743 len += scnprintf(msg + len, sizeof(msg) - len, " 0x%x", value); 744 } 745 746 dev_printk(level, sdev->dev, "extended rom status: %s", msg); 747 748} 749 750void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags) 751{ 752 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; 753 struct sof_ipc_dsp_oops_xtensa xoops; 754 struct sof_ipc_panic_info panic_info; 755 u32 stack[HDA_DSP_STACK_DUMP_SIZE]; 756 757 /* print ROM/FW status */ 758 hda_dsp_get_state(sdev, level); 759 760 /* The firmware register dump only available with IPC3 */ 761 if (flags & SOF_DBG_DUMP_REGS && sdev->pdata->ipc_type == SOF_IPC_TYPE_3) { 762 u32 status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_STATUS); 763 u32 panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP); 764 765 hda_dsp_get_registers(sdev, &xoops, &panic_info, stack, 766 HDA_DSP_STACK_DUMP_SIZE); 767 sof_print_oops_and_stack(sdev, level, status, panic, &xoops, 768 &panic_info, stack, HDA_DSP_STACK_DUMP_SIZE); 769 } else { 770 hda_dsp_dump_ext_rom_status(sdev, level, flags); 771 } 772} 773 774void hda_ipc4_dsp_dump(struct snd_sof_dev *sdev, u32 flags) 775{ 776 char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR; 777 778 /* print ROM/FW status */ 779 hda_dsp_get_state(sdev, level); 780 781 if (flags & SOF_DBG_DUMP_REGS) 782 sof_ipc4_intel_dump_telemetry_state(sdev, flags); 783 else 784 hda_dsp_dump_ext_rom_status(sdev, level, flags); 785} 786 787static bool hda_check_ipc_irq(struct snd_sof_dev *sdev) 788{ 789 const struct sof_intel_dsp_desc *chip; 790 791 chip = get_chip_info(sdev->pdata); 792 if (chip && chip->check_ipc_irq) 793 return chip->check_ipc_irq(sdev); 794 795 return false; 796} 797 798void hda_ipc_irq_dump(struct snd_sof_dev *sdev) 799{ 800 u32 adspis; 801 u32 intsts; 802 u32 intctl; 803 u32 ppsts; 804 u8 rirbsts; 805 806 /* read key IRQ stats and config registers */ 807 adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS); 808 intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS); 809 intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL); 810 ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS); 811 rirbsts = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, AZX_REG_RIRBSTS); 812 813 dev_err(sdev->dev, "hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n", 814 intsts, intctl, rirbsts); 815 dev_err(sdev->dev, "dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n", ppsts, adspis); 816} 817 818void hda_ipc_dump(struct snd_sof_dev *sdev) 819{ 820 u32 hipcie; 821 u32 hipct; 822 u32 hipcctl; 823 824 hda_ipc_irq_dump(sdev); 825 826 /* read IPC status */ 827 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); 828 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); 829 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL); 830 831 /* dump the IPC regs */ 832 /* TODO: parse the raw msg */ 833 dev_err(sdev->dev, "host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n", 834 hipcie, hipct, hipcctl); 835} 836 837void hda_ipc4_dump(struct snd_sof_dev *sdev) 838{ 839 u32 hipci, hipcie, hipct, hipcte, hipcctl; 840 841 hda_ipc_irq_dump(sdev); 842 843 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI); 844 hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE); 845 hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT); 846 hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCTE); 847 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL); 848 849 /* dump the IPC regs */ 850 /* TODO: parse the raw msg */ 851 dev_err(sdev->dev, "Host IPC initiator: %#x|%#x, target: %#x|%#x, ctl: %#x\n", 852 hipci, hipcie, hipct, hipcte, hipcctl); 853} 854 855bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev) 856{ 857 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 858 const struct sof_intel_dsp_desc *chip = hda->desc; 859 u32 val; 860 861 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->ipc_req); 862 863 return !!(val & chip->ipc_req_mask); 864} 865 866static int hda_init(struct snd_sof_dev *sdev) 867{ 868 struct hda_bus *hbus; 869 struct hdac_bus *bus; 870 struct pci_dev *pci = to_pci_dev(sdev->dev); 871 int ret; 872 873 hbus = sof_to_hbus(sdev); 874 bus = sof_to_bus(sdev); 875 876 /* HDA bus init */ 877 sof_hda_bus_init(sdev, &pci->dev); 878 879 if (sof_hda_position_quirk == SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS) 880 bus->use_posbuf = 0; 881 else 882 bus->use_posbuf = 1; 883 bus->bdl_pos_adj = 0; 884 bus->sync_write = 1; 885 886 mutex_init(&hbus->prepare_mutex); 887 hbus->pci = pci; 888 hbus->mixer_assigned = -1; 889 hbus->modelname = hda_model; 890 891 /* initialise hdac bus */ 892 bus->addr = pci_resource_start(pci, 0); 893 bus->remap_addr = pci_ioremap_bar(pci, 0); 894 if (!bus->remap_addr) { 895 dev_err(bus->dev, "error: ioremap error\n"); 896 return -ENXIO; 897 } 898 899 /* HDA base */ 900 sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr; 901 902 /* init i915 and HDMI codecs */ 903 ret = hda_codec_i915_init(sdev); 904 if (ret < 0 && ret != -ENODEV) { 905 dev_err_probe(sdev->dev, ret, "init of i915 and HDMI codec failed\n"); 906 goto out; 907 } 908 909 /* get controller capabilities */ 910 ret = hda_dsp_ctrl_get_caps(sdev); 911 if (ret < 0) { 912 dev_err(sdev->dev, "error: get caps error\n"); 913 hda_codec_i915_exit(sdev); 914 } 915 916out: 917 if (ret < 0) 918 iounmap(sof_to_bus(sdev)->remap_addr); 919 920 return ret; 921} 922 923static int check_dmic_num(struct snd_sof_dev *sdev) 924{ 925 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 926 struct nhlt_acpi_table *nhlt; 927 int dmic_num = 0; 928 929 nhlt = hdev->nhlt; 930 if (nhlt) 931 dmic_num = intel_nhlt_get_dmic_geo(sdev->dev, nhlt); 932 933 /* allow for module parameter override */ 934 if (dmic_num_override != -1) { 935 dev_dbg(sdev->dev, 936 "overriding DMICs detected in NHLT tables %d by kernel param %d\n", 937 dmic_num, dmic_num_override); 938 dmic_num = dmic_num_override; 939 } 940 941 if (dmic_num < 0 || dmic_num > 4) { 942 dev_dbg(sdev->dev, "invalid dmic_number %d\n", dmic_num); 943 dmic_num = 0; 944 } 945 946 return dmic_num; 947} 948 949static int check_nhlt_ssp_mask(struct snd_sof_dev *sdev) 950{ 951 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 952 struct nhlt_acpi_table *nhlt; 953 int ssp_mask = 0; 954 955 nhlt = hdev->nhlt; 956 if (!nhlt) 957 return ssp_mask; 958 959 if (intel_nhlt_has_endpoint_type(nhlt, NHLT_LINK_SSP)) { 960 ssp_mask = intel_nhlt_ssp_endpoint_mask(nhlt, NHLT_DEVICE_I2S); 961 if (ssp_mask) 962 dev_info(sdev->dev, "NHLT_DEVICE_I2S detected, ssp_mask %#x\n", ssp_mask); 963 } 964 965 return ssp_mask; 966} 967 968static int check_nhlt_ssp_mclk_mask(struct snd_sof_dev *sdev, int ssp_num) 969{ 970 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 971 struct nhlt_acpi_table *nhlt; 972 973 nhlt = hdev->nhlt; 974 if (!nhlt) 975 return 0; 976 977 return intel_nhlt_ssp_mclk_mask(nhlt, ssp_num); 978} 979 980#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) || IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 981 982static const char *fixup_tplg_name(struct snd_sof_dev *sdev, 983 const char *sof_tplg_filename, 984 const char *idisp_str, 985 const char *dmic_str) 986{ 987 const char *tplg_filename = NULL; 988 char *filename, *tmp; 989 const char *split_ext; 990 991 filename = kstrdup(sof_tplg_filename, GFP_KERNEL); 992 if (!filename) 993 return NULL; 994 995 /* this assumes a .tplg extension */ 996 tmp = filename; 997 split_ext = strsep(&tmp, "."); 998 if (split_ext) 999 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1000 "%s%s%s.tplg", 1001 split_ext, idisp_str, dmic_str); 1002 kfree(filename); 1003 1004 return tplg_filename; 1005} 1006 1007static int dmic_detect_topology_fixup(struct snd_sof_dev *sdev, 1008 const char **tplg_filename, 1009 const char *idisp_str, 1010 int *dmic_found, 1011 bool tplg_fixup) 1012{ 1013 const char *dmic_str; 1014 int dmic_num; 1015 1016 /* first check for DMICs (using NHLT or module parameter) */ 1017 dmic_num = check_dmic_num(sdev); 1018 1019 switch (dmic_num) { 1020 case 1: 1021 dmic_str = "-1ch"; 1022 break; 1023 case 2: 1024 dmic_str = "-2ch"; 1025 break; 1026 case 3: 1027 dmic_str = "-3ch"; 1028 break; 1029 case 4: 1030 dmic_str = "-4ch"; 1031 break; 1032 default: 1033 dmic_num = 0; 1034 dmic_str = ""; 1035 break; 1036 } 1037 1038 if (tplg_fixup) { 1039 const char *default_tplg_filename = *tplg_filename; 1040 const char *fixed_tplg_filename; 1041 1042 fixed_tplg_filename = fixup_tplg_name(sdev, default_tplg_filename, 1043 idisp_str, dmic_str); 1044 if (!fixed_tplg_filename) 1045 return -ENOMEM; 1046 *tplg_filename = fixed_tplg_filename; 1047 } 1048 1049 dev_info(sdev->dev, "DMICs detected in NHLT tables: %d\n", dmic_num); 1050 *dmic_found = dmic_num; 1051 1052 return 0; 1053} 1054#endif 1055 1056static int hda_init_caps(struct snd_sof_dev *sdev) 1057{ 1058 u32 interface_mask = hda_get_interface_mask(sdev); 1059 struct hdac_bus *bus = sof_to_bus(sdev); 1060 struct snd_sof_pdata *pdata = sdev->pdata; 1061 struct sof_intel_hda_dev *hdev = pdata->hw_pdata; 1062 u32 link_mask; 1063 int ret = 0; 1064 1065 /* check if dsp is there */ 1066 if (bus->ppcap) 1067 dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n"); 1068 1069 /* Init HDA controller after i915 init */ 1070 ret = hda_dsp_ctrl_init_chip(sdev); 1071 if (ret < 0) { 1072 dev_err(bus->dev, "error: init chip failed with ret: %d\n", 1073 ret); 1074 return ret; 1075 } 1076 1077 hda_bus_ml_init(bus); 1078 1079 /* Skip SoundWire if it is not supported */ 1080 if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH))) 1081 goto skip_soundwire; 1082 1083 /* scan SoundWire capabilities exposed by DSDT */ 1084 ret = hda_sdw_acpi_scan(sdev); 1085 if (ret < 0) { 1086 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n"); 1087 goto skip_soundwire; 1088 } 1089 1090 link_mask = hdev->info.link_mask; 1091 if (!link_mask) { 1092 dev_dbg(sdev->dev, "skipping SoundWire, no links enabled\n"); 1093 goto skip_soundwire; 1094 } 1095 1096 /* 1097 * probe/allocate SoundWire resources. 1098 * The hardware configuration takes place in hda_sdw_startup 1099 * after power rails are enabled. 1100 * It's entirely possible to have a mix of I2S/DMIC/SoundWire 1101 * devices, so we allocate the resources in all cases. 1102 */ 1103 ret = hda_sdw_probe(sdev); 1104 if (ret < 0) { 1105 dev_err(sdev->dev, "error: SoundWire probe error\n"); 1106 return ret; 1107 } 1108 1109skip_soundwire: 1110 1111 /* create codec instances */ 1112 hda_codec_probe_bus(sdev); 1113 1114 if (!HDA_IDISP_CODEC(bus->codec_mask)) 1115 hda_codec_i915_display_power(sdev, false); 1116 1117 hda_bus_ml_put_all(bus); 1118 1119 return 0; 1120} 1121 1122static irqreturn_t hda_dsp_interrupt_handler(int irq, void *context) 1123{ 1124 struct snd_sof_dev *sdev = context; 1125 1126 /* 1127 * Get global interrupt status. It includes all hardware interrupt 1128 * sources in the Intel HD Audio controller. 1129 */ 1130 if (snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS) & 1131 SOF_HDA_INTSTS_GIS) { 1132 1133 /* disable GIE interrupt */ 1134 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 1135 SOF_HDA_INTCTL, 1136 SOF_HDA_INT_GLOBAL_EN, 1137 0); 1138 1139 return IRQ_WAKE_THREAD; 1140 } 1141 1142 return IRQ_NONE; 1143} 1144 1145static irqreturn_t hda_dsp_interrupt_thread(int irq, void *context) 1146{ 1147 struct snd_sof_dev *sdev = context; 1148 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 1149 1150 /* deal with streams and controller first */ 1151 if (hda_dsp_check_stream_irq(sdev)) { 1152 trace_sof_intel_hda_irq(sdev, "stream"); 1153 hda_dsp_stream_threaded_handler(irq, sdev); 1154 } 1155 1156 if (hda_check_ipc_irq(sdev)) { 1157 trace_sof_intel_hda_irq(sdev, "ipc"); 1158 sof_ops(sdev)->irq_thread(irq, sdev); 1159 } 1160 1161 if (hda_dsp_check_sdw_irq(sdev)) { 1162 trace_sof_intel_hda_irq(sdev, "sdw"); 1163 hda_dsp_sdw_thread(irq, hdev->sdw); 1164 } 1165 1166 if (hda_sdw_check_wakeen_irq(sdev)) { 1167 trace_sof_intel_hda_irq(sdev, "wakeen"); 1168 hda_sdw_process_wakeen(sdev); 1169 } 1170 1171 hda_codec_check_for_state_change(sdev); 1172 1173 /* enable GIE interrupt */ 1174 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, 1175 SOF_HDA_INTCTL, 1176 SOF_HDA_INT_GLOBAL_EN, 1177 SOF_HDA_INT_GLOBAL_EN); 1178 1179 return IRQ_HANDLED; 1180} 1181 1182int hda_dsp_probe_early(struct snd_sof_dev *sdev) 1183{ 1184 struct pci_dev *pci = to_pci_dev(sdev->dev); 1185 struct sof_intel_hda_dev *hdev; 1186 const struct sof_intel_dsp_desc *chip; 1187 int ret = 0; 1188 1189 if (!sdev->dspless_mode_selected) { 1190 /* 1191 * detect DSP by checking class/subclass/prog-id information 1192 * class=04 subclass 03 prog-if 00: no DSP, legacy driver is required 1193 * class=04 subclass 01 prog-if 00: DSP is present 1194 * (and may be required e.g. for DMIC or SSP support) 1195 * class=04 subclass 03 prog-if 80: either of DSP or legacy mode works 1196 */ 1197 if (pci->class == 0x040300) { 1198 dev_err(sdev->dev, "the DSP is not enabled on this platform, aborting probe\n"); 1199 return -ENODEV; 1200 } else if (pci->class != 0x040100 && pci->class != 0x040380) { 1201 dev_err(sdev->dev, "unknown PCI class/subclass/prog-if 0x%06x found, aborting probe\n", 1202 pci->class); 1203 return -ENODEV; 1204 } 1205 dev_info(sdev->dev, "DSP detected with PCI class/subclass/prog-if 0x%06x\n", 1206 pci->class); 1207 } 1208 1209 chip = get_chip_info(sdev->pdata); 1210 if (!chip) { 1211 dev_err(sdev->dev, "error: no such device supported, chip id:%x\n", 1212 pci->device); 1213 ret = -EIO; 1214 goto err; 1215 } 1216 1217 sdev->num_cores = chip->cores_num; 1218 1219 hdev = devm_kzalloc(sdev->dev, sizeof(*hdev), GFP_KERNEL); 1220 if (!hdev) 1221 return -ENOMEM; 1222 sdev->pdata->hw_pdata = hdev; 1223 hdev->desc = chip; 1224 ret = hda_init(sdev); 1225 1226err: 1227 return ret; 1228} 1229 1230int hda_dsp_probe(struct snd_sof_dev *sdev) 1231{ 1232 struct pci_dev *pci = to_pci_dev(sdev->dev); 1233 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 1234 const struct sof_intel_dsp_desc *chip; 1235 int ret = 0; 1236 1237 hdev->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 1238 PLATFORM_DEVID_NONE, 1239 NULL, 0); 1240 if (IS_ERR(hdev->dmic_dev)) { 1241 dev_err(sdev->dev, "error: failed to create DMIC device\n"); 1242 return PTR_ERR(hdev->dmic_dev); 1243 } 1244 1245 /* 1246 * use position update IPC if either it is forced 1247 * or we don't have other choice 1248 */ 1249#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_FORCE_IPC_POSITION) 1250 hdev->no_ipc_position = 0; 1251#else 1252 hdev->no_ipc_position = sof_ops(sdev)->pcm_pointer ? 1 : 0; 1253#endif 1254 1255 if (sdev->dspless_mode_selected) 1256 hdev->no_ipc_position = 1; 1257 1258 if (sdev->dspless_mode_selected) 1259 goto skip_dsp_setup; 1260 1261 /* DSP base */ 1262 sdev->bar[HDA_DSP_BAR] = pci_ioremap_bar(pci, HDA_DSP_BAR); 1263 if (!sdev->bar[HDA_DSP_BAR]) { 1264 dev_err(sdev->dev, "error: ioremap error\n"); 1265 ret = -ENXIO; 1266 goto hdac_bus_unmap; 1267 } 1268 1269 sdev->mmio_bar = HDA_DSP_BAR; 1270 sdev->mailbox_bar = HDA_DSP_BAR; 1271skip_dsp_setup: 1272 1273 /* allow 64bit DMA address if supported by H/W */ 1274 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(64))) { 1275 dev_dbg(sdev->dev, "DMA mask is 32 bit\n"); 1276 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1277 } 1278 dma_set_max_seg_size(&pci->dev, UINT_MAX); 1279 1280 /* init streams */ 1281 ret = hda_dsp_stream_init(sdev); 1282 if (ret < 0) { 1283 dev_err(sdev->dev, "error: failed to init streams\n"); 1284 /* 1285 * not all errors are due to memory issues, but trying 1286 * to free everything does not harm 1287 */ 1288 goto free_streams; 1289 } 1290 1291 /* 1292 * register our IRQ 1293 * let's try to enable msi firstly 1294 * if it fails, use legacy interrupt mode 1295 * TODO: support msi multiple vectors 1296 */ 1297 if (hda_use_msi && pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI) > 0) { 1298 dev_info(sdev->dev, "use msi interrupt mode\n"); 1299 sdev->ipc_irq = pci_irq_vector(pci, 0); 1300 /* initialised to "false" by kzalloc() */ 1301 sdev->msi_enabled = true; 1302 } 1303 1304 if (!sdev->msi_enabled) { 1305 dev_info(sdev->dev, "use legacy interrupt mode\n"); 1306 /* 1307 * in IO-APIC mode, hda->irq and ipc_irq are using the same 1308 * irq number of pci->irq 1309 */ 1310 sdev->ipc_irq = pci->irq; 1311 } 1312 1313 dev_dbg(sdev->dev, "using IPC IRQ %d\n", sdev->ipc_irq); 1314 ret = request_threaded_irq(sdev->ipc_irq, hda_dsp_interrupt_handler, 1315 hda_dsp_interrupt_thread, 1316 IRQF_SHARED, "AudioDSP", sdev); 1317 if (ret < 0) { 1318 dev_err(sdev->dev, "error: failed to register IPC IRQ %d\n", 1319 sdev->ipc_irq); 1320 goto free_irq_vector; 1321 } 1322 1323 pci_set_master(pci); 1324 synchronize_irq(pci->irq); 1325 1326 /* 1327 * clear TCSEL to clear playback on some HD Audio 1328 * codecs. PCI TCSEL is defined in the Intel manuals. 1329 */ 1330 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0); 1331 1332 /* init HDA capabilities */ 1333 ret = hda_init_caps(sdev); 1334 if (ret < 0) 1335 goto free_ipc_irq; 1336 1337 if (!sdev->dspless_mode_selected) { 1338 /* enable ppcap interrupt */ 1339 hda_dsp_ctrl_ppcap_enable(sdev, true); 1340 hda_dsp_ctrl_ppcap_int_enable(sdev, true); 1341 1342 /* set default mailbox offset for FW ready message */ 1343 sdev->dsp_box.offset = HDA_DSP_MBOX_UPLINK_OFFSET; 1344 1345 INIT_DELAYED_WORK(&hdev->d0i3_work, hda_dsp_d0i3_work); 1346 } 1347 1348 chip = get_chip_info(sdev->pdata); 1349 if (chip && chip->hw_ip_version >= SOF_INTEL_ACE_2_0) { 1350 ret = hda_sdw_startup(sdev); 1351 if (ret < 0) { 1352 dev_err(sdev->dev, "could not startup SoundWire links\n"); 1353 goto disable_pp_cap; 1354 } 1355 1356 hda_sdw_int_enable(sdev, true); 1357 } 1358 1359 init_waitqueue_head(&hdev->waitq); 1360 1361 hdev->nhlt = intel_nhlt_init(sdev->dev); 1362 1363 return 0; 1364 1365disable_pp_cap: 1366 if (!sdev->dspless_mode_selected) { 1367 hda_dsp_ctrl_ppcap_int_enable(sdev, false); 1368 hda_dsp_ctrl_ppcap_enable(sdev, false); 1369 } 1370free_ipc_irq: 1371 free_irq(sdev->ipc_irq, sdev); 1372free_irq_vector: 1373 if (sdev->msi_enabled) 1374 pci_free_irq_vectors(pci); 1375free_streams: 1376 hda_dsp_stream_free(sdev); 1377/* dsp_unmap: not currently used */ 1378 if (!sdev->dspless_mode_selected) 1379 iounmap(sdev->bar[HDA_DSP_BAR]); 1380hdac_bus_unmap: 1381 platform_device_unregister(hdev->dmic_dev); 1382 1383 return ret; 1384} 1385 1386void hda_dsp_remove(struct snd_sof_dev *sdev) 1387{ 1388 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 1389 const struct sof_intel_dsp_desc *chip = hda->desc; 1390 struct pci_dev *pci = to_pci_dev(sdev->dev); 1391 struct nhlt_acpi_table *nhlt = hda->nhlt; 1392 1393 if (nhlt) 1394 intel_nhlt_free(nhlt); 1395 1396 if (!sdev->dspless_mode_selected) 1397 /* cancel any attempt for DSP D0I3 */ 1398 cancel_delayed_work_sync(&hda->d0i3_work); 1399 1400 hda_codec_device_remove(sdev); 1401 1402 hda_sdw_exit(sdev); 1403 1404 if (!IS_ERR_OR_NULL(hda->dmic_dev)) 1405 platform_device_unregister(hda->dmic_dev); 1406 1407 if (!sdev->dspless_mode_selected) { 1408 /* disable DSP IRQ */ 1409 hda_dsp_ctrl_ppcap_int_enable(sdev, false); 1410 } 1411 1412 /* disable CIE and GIE interrupts */ 1413 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL, 1414 SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN, 0); 1415 1416 if (sdev->dspless_mode_selected) 1417 goto skip_disable_dsp; 1418 1419 /* no need to check for error as the DSP will be disabled anyway */ 1420 if (chip && chip->power_down_dsp) 1421 chip->power_down_dsp(sdev); 1422 1423 /* disable DSP */ 1424 hda_dsp_ctrl_ppcap_enable(sdev, false); 1425 1426skip_disable_dsp: 1427 free_irq(sdev->ipc_irq, sdev); 1428 if (sdev->msi_enabled) 1429 pci_free_irq_vectors(pci); 1430 1431 hda_dsp_stream_free(sdev); 1432 1433 hda_bus_ml_free(sof_to_bus(sdev)); 1434 1435 if (!sdev->dspless_mode_selected) 1436 iounmap(sdev->bar[HDA_DSP_BAR]); 1437} 1438 1439void hda_dsp_remove_late(struct snd_sof_dev *sdev) 1440{ 1441 iounmap(sof_to_bus(sdev)->remap_addr); 1442 sof_hda_bus_exit(sdev); 1443 hda_codec_i915_exit(sdev); 1444} 1445 1446int hda_power_down_dsp(struct snd_sof_dev *sdev) 1447{ 1448 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata; 1449 const struct sof_intel_dsp_desc *chip = hda->desc; 1450 1451 return hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask); 1452} 1453 1454#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) 1455static void hda_generic_machine_select(struct snd_sof_dev *sdev, 1456 struct snd_soc_acpi_mach **mach) 1457{ 1458 struct hdac_bus *bus = sof_to_bus(sdev); 1459 struct snd_soc_acpi_mach_params *mach_params; 1460 struct snd_soc_acpi_mach *hda_mach; 1461 struct snd_sof_pdata *pdata = sdev->pdata; 1462 const char *tplg_filename; 1463 const char *idisp_str; 1464 int dmic_num = 0; 1465 int codec_num = 0; 1466 int ret; 1467 int i; 1468 1469 /* codec detection */ 1470 if (!bus->codec_mask) { 1471 dev_info(bus->dev, "no hda codecs found!\n"); 1472 } else { 1473 dev_info(bus->dev, "hda codecs found, mask %lx\n", 1474 bus->codec_mask); 1475 1476 for (i = 0; i < HDA_MAX_CODECS; i++) { 1477 if (bus->codec_mask & (1 << i)) 1478 codec_num++; 1479 } 1480 1481 /* 1482 * If no machine driver is found, then: 1483 * 1484 * generic hda machine driver can handle: 1485 * - one HDMI codec, and/or 1486 * - one external HDAudio codec 1487 */ 1488 if (!*mach && codec_num <= 2) { 1489 bool tplg_fixup; 1490 1491 hda_mach = snd_soc_acpi_intel_hda_machines; 1492 1493 dev_info(bus->dev, "using HDA machine driver %s now\n", 1494 hda_mach->drv_name); 1495 1496 if (codec_num == 1 && HDA_IDISP_CODEC(bus->codec_mask)) 1497 idisp_str = "-idisp"; 1498 else 1499 idisp_str = ""; 1500 1501 /* topology: use the info from hda_machines */ 1502 if (pdata->tplg_filename) { 1503 tplg_fixup = false; 1504 tplg_filename = pdata->tplg_filename; 1505 } else { 1506 tplg_fixup = true; 1507 tplg_filename = hda_mach->sof_tplg_filename; 1508 } 1509 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, idisp_str, &dmic_num, 1510 tplg_fixup); 1511 if (ret < 0) 1512 return; 1513 1514 hda_mach->mach_params.dmic_num = dmic_num; 1515 pdata->tplg_filename = tplg_filename; 1516 1517 if (codec_num == 2 || 1518 (codec_num == 1 && !HDA_IDISP_CODEC(bus->codec_mask))) { 1519 /* 1520 * Prevent SoundWire links from starting when an external 1521 * HDaudio codec is used 1522 */ 1523 hda_mach->mach_params.link_mask = 0; 1524 } else { 1525 /* 1526 * Allow SoundWire links to start when no external HDaudio codec 1527 * was detected. This will not create a SoundWire card but 1528 * will help detect if any SoundWire codec reports as ATTACHED. 1529 */ 1530 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata; 1531 1532 hda_mach->mach_params.link_mask = hdev->info.link_mask; 1533 } 1534 1535 *mach = hda_mach; 1536 } 1537 } 1538 1539 /* used by hda machine driver to create dai links */ 1540 if (*mach) { 1541 mach_params = &(*mach)->mach_params; 1542 mach_params->codec_mask = bus->codec_mask; 1543 mach_params->common_hdmi_codec_drv = true; 1544 } 1545} 1546#else 1547static void hda_generic_machine_select(struct snd_sof_dev *sdev, 1548 struct snd_soc_acpi_mach **mach) 1549{ 1550} 1551#endif 1552 1553#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) 1554 1555static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev) 1556{ 1557 struct snd_sof_pdata *pdata = sdev->pdata; 1558 const struct snd_soc_acpi_link_adr *link; 1559 struct snd_soc_acpi_mach *mach; 1560 struct sof_intel_hda_dev *hdev; 1561 u32 link_mask; 1562 int i; 1563 1564 hdev = pdata->hw_pdata; 1565 link_mask = hdev->info.link_mask; 1566 1567 /* 1568 * Select SoundWire machine driver if needed using the 1569 * alternate tables. This case deals with SoundWire-only 1570 * machines, for mixed cases with I2C/I2S the detection relies 1571 * on the HID list. 1572 */ 1573 if (link_mask) { 1574 for (mach = pdata->desc->alt_machines; 1575 mach && mach->link_mask; mach++) { 1576 /* 1577 * On some platforms such as Up Extreme all links 1578 * are enabled but only one link can be used by 1579 * external codec. Instead of exact match of two masks, 1580 * first check whether link_mask of mach is subset of 1581 * link_mask supported by hw and then go on searching 1582 * link_adr 1583 */ 1584 if (~link_mask & mach->link_mask) 1585 continue; 1586 1587 /* No need to match adr if there is no links defined */ 1588 if (!mach->links) 1589 break; 1590 1591 link = mach->links; 1592 for (i = 0; i < hdev->info.count && link->num_adr; 1593 i++, link++) { 1594 /* 1595 * Try next machine if any expected Slaves 1596 * are not found on this link. 1597 */ 1598 if (!snd_soc_acpi_sdw_link_slaves_found(sdev->dev, link, 1599 hdev->sdw->ids, 1600 hdev->sdw->num_slaves)) 1601 break; 1602 } 1603 /* Found if all Slaves are checked */ 1604 if (i == hdev->info.count || !link->num_adr) 1605 break; 1606 } 1607 if (mach && mach->link_mask) { 1608 int dmic_num = 0; 1609 bool tplg_fixup; 1610 const char *tplg_filename; 1611 1612 mach->mach_params.links = mach->links; 1613 mach->mach_params.link_mask = mach->link_mask; 1614 mach->mach_params.platform = dev_name(sdev->dev); 1615 1616 if (pdata->tplg_filename) { 1617 tplg_fixup = false; 1618 } else { 1619 tplg_fixup = true; 1620 tplg_filename = mach->sof_tplg_filename; 1621 } 1622 1623 /* 1624 * DMICs use up to 4 pins and are typically pin-muxed with SoundWire 1625 * link 2 and 3, or link 1 and 2, thus we only try to enable dmics 1626 * if all conditions are true: 1627 * a) 2 or fewer links are used by SoundWire 1628 * b) the NHLT table reports the presence of microphones 1629 */ 1630 if (hweight_long(mach->link_mask) <= 2) { 1631 int ret; 1632 1633 ret = dmic_detect_topology_fixup(sdev, &tplg_filename, "", 1634 &dmic_num, tplg_fixup); 1635 if (ret < 0) 1636 return NULL; 1637 } 1638 if (tplg_fixup) 1639 pdata->tplg_filename = tplg_filename; 1640 mach->mach_params.dmic_num = dmic_num; 1641 1642 dev_dbg(sdev->dev, 1643 "SoundWire machine driver %s topology %s\n", 1644 mach->drv_name, 1645 pdata->tplg_filename); 1646 1647 return mach; 1648 } 1649 1650 dev_info(sdev->dev, "No SoundWire machine driver found\n"); 1651 } 1652 1653 return NULL; 1654} 1655#else 1656static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev) 1657{ 1658 return NULL; 1659} 1660#endif 1661 1662void hda_set_mach_params(struct snd_soc_acpi_mach *mach, 1663 struct snd_sof_dev *sdev) 1664{ 1665 struct snd_sof_pdata *pdata = sdev->pdata; 1666 const struct sof_dev_desc *desc = pdata->desc; 1667 struct snd_soc_acpi_mach_params *mach_params; 1668 1669 mach_params = &mach->mach_params; 1670 mach_params->platform = dev_name(sdev->dev); 1671 if (IS_ENABLED(CONFIG_SND_SOC_SOF_NOCODEC_DEBUG_SUPPORT) && 1672 sof_debug_check_flag(SOF_DBG_FORCE_NOCODEC)) 1673 mach_params->num_dai_drivers = SOF_SKL_NUM_DAIS_NOCODEC; 1674 else 1675 mach_params->num_dai_drivers = desc->ops->num_drv; 1676 mach_params->dai_drivers = desc->ops->drv; 1677} 1678 1679struct snd_soc_acpi_mach *hda_machine_select(struct snd_sof_dev *sdev) 1680{ 1681 u32 interface_mask = hda_get_interface_mask(sdev); 1682 struct snd_sof_pdata *sof_pdata = sdev->pdata; 1683 const struct sof_dev_desc *desc = sof_pdata->desc; 1684 struct snd_soc_acpi_mach *mach = NULL; 1685 const char *tplg_filename; 1686 1687 /* Try I2S or DMIC if it is supported */ 1688 if (interface_mask & (BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC))) 1689 mach = snd_soc_acpi_find_machine(desc->machines); 1690 1691 if (mach) { 1692 bool add_extension = false; 1693 bool tplg_fixup = false; 1694 1695 /* 1696 * If tplg file name is overridden, use it instead of 1697 * the one set in mach table 1698 */ 1699 if (!sof_pdata->tplg_filename) { 1700 sof_pdata->tplg_filename = mach->sof_tplg_filename; 1701 tplg_fixup = true; 1702 } 1703 1704 /* report to machine driver if any DMICs are found */ 1705 mach->mach_params.dmic_num = check_dmic_num(sdev); 1706 1707 if (tplg_fixup && 1708 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_DMIC_NUMBER && 1709 mach->mach_params.dmic_num) { 1710 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1711 "%s%s%d%s", 1712 sof_pdata->tplg_filename, 1713 "-dmic", 1714 mach->mach_params.dmic_num, 1715 "ch"); 1716 if (!tplg_filename) 1717 return NULL; 1718 1719 sof_pdata->tplg_filename = tplg_filename; 1720 add_extension = true; 1721 } 1722 1723 if (mach->link_mask) { 1724 mach->mach_params.links = mach->links; 1725 mach->mach_params.link_mask = mach->link_mask; 1726 } 1727 1728 /* report SSP link mask to machine driver */ 1729 mach->mach_params.i2s_link_mask = check_nhlt_ssp_mask(sdev); 1730 1731 if (tplg_fixup && 1732 mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_NUMBER && 1733 mach->mach_params.i2s_link_mask) { 1734 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata); 1735 int ssp_num; 1736 int mclk_mask; 1737 1738 if (hweight_long(mach->mach_params.i2s_link_mask) > 1 && 1739 !(mach->tplg_quirk_mask & SND_SOC_ACPI_TPLG_INTEL_SSP_MSB)) 1740 dev_warn(sdev->dev, "More than one SSP exposed by NHLT, choosing MSB\n"); 1741 1742 /* fls returns 1-based results, SSPs indices are 0-based */ 1743 ssp_num = fls(mach->mach_params.i2s_link_mask) - 1; 1744 1745 if (ssp_num >= chip->ssp_count) { 1746 dev_err(sdev->dev, "Invalid SSP %d, max on this platform is %d\n", 1747 ssp_num, chip->ssp_count); 1748 return NULL; 1749 } 1750 1751 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1752 "%s%s%d", 1753 sof_pdata->tplg_filename, 1754 "-ssp", 1755 ssp_num); 1756 if (!tplg_filename) 1757 return NULL; 1758 1759 sof_pdata->tplg_filename = tplg_filename; 1760 add_extension = true; 1761 1762 mclk_mask = check_nhlt_ssp_mclk_mask(sdev, ssp_num); 1763 1764 if (mclk_mask < 0) { 1765 dev_err(sdev->dev, "Invalid MCLK configuration\n"); 1766 return NULL; 1767 } 1768 1769 dev_dbg(sdev->dev, "MCLK mask %#x found in NHLT\n", mclk_mask); 1770 1771 if (mclk_mask) { 1772 dev_info(sdev->dev, "Overriding topology with MCLK mask %#x from NHLT\n", mclk_mask); 1773 sdev->mclk_id_override = true; 1774 sdev->mclk_id_quirk = (mclk_mask & BIT(0)) ? 0 : 1; 1775 } 1776 } 1777 1778 if (tplg_fixup && add_extension) { 1779 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL, 1780 "%s%s", 1781 sof_pdata->tplg_filename, 1782 ".tplg"); 1783 if (!tplg_filename) 1784 return NULL; 1785 1786 sof_pdata->tplg_filename = tplg_filename; 1787 } 1788 1789 /* check if mclk_id should be modified from topology defaults */ 1790 if (mclk_id_override >= 0) { 1791 dev_info(sdev->dev, "Overriding topology with MCLK %d from kernel_parameter\n", mclk_id_override); 1792 sdev->mclk_id_override = true; 1793 sdev->mclk_id_quirk = mclk_id_override; 1794 } 1795 } 1796 1797 /* If I2S fails, try SoundWire if it is supported */ 1798 if (!mach && (interface_mask & BIT(SOF_DAI_INTEL_ALH))) 1799 mach = hda_sdw_machine_select(sdev); 1800 1801 /* 1802 * Choose HDA generic machine driver if mach is NULL. 1803 * Otherwise, set certain mach params. 1804 */ 1805 hda_generic_machine_select(sdev, &mach); 1806 if (!mach) 1807 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n"); 1808 1809 return mach; 1810} 1811 1812int hda_pci_intel_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1813{ 1814 int ret; 1815 1816 ret = snd_intel_dsp_driver_probe(pci); 1817 if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) { 1818 dev_dbg(&pci->dev, "SOF PCI driver not selected, aborting probe\n"); 1819 return -ENODEV; 1820 } 1821 1822 return sof_pci_probe(pci, pci_id); 1823} 1824EXPORT_SYMBOL_NS(hda_pci_intel_probe, SND_SOC_SOF_INTEL_HDA_COMMON); 1825 1826int hda_register_clients(struct snd_sof_dev *sdev) 1827{ 1828 return hda_probes_register(sdev); 1829} 1830 1831void hda_unregister_clients(struct snd_sof_dev *sdev) 1832{ 1833 hda_probes_unregister(sdev); 1834} 1835 1836MODULE_LICENSE("Dual BSD/GPL"); 1837MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV); 1838MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC); 1839MODULE_IMPORT_NS(SND_SOC_SOF_HDA_AUDIO_CODEC_I915); 1840MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA); 1841MODULE_IMPORT_NS(SND_INTEL_SOUNDWIRE_ACPI); 1842MODULE_IMPORT_NS(SOUNDWIRE_INTEL_INIT); 1843MODULE_IMPORT_NS(SOUNDWIRE_INTEL); 1844MODULE_IMPORT_NS(SND_SOC_SOF_HDA_MLINK); 1845