Searched refs:mclk (Results 1 - 25 of 317) sorted by relevance

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/linux-master/drivers/media/dvb-frontends/
H A Dmn88443x.h19 struct clk *mclk; member in struct:mn88443x_config
H A Dstv6110.h29 u32 mclk; member in struct:stv6110_config
H A Dstv0900_sw.c42 max_carrier /= intp->mclk / 1000;
69 max_carrier /= intp->mclk / 1000;
75 freq_inc /= intp->mclk >> 10;
135 max_carrier /= intp->mclk / 1000;
295 u32 mclk,
310 intval1 = (mclk) >> 16;
313 rem1 = (mclk) % 0x10000;
323 u32 mclk, u32 srate,
328 dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
333 symb /= (mclk >> 1
294 stv0900_get_symbol_rate(struct stv0900_internal *intp, u32 mclk, enum fe_stv0900_demod_num demod) argument
322 stv0900_set_symbol_rate(struct stv0900_internal *intp, u32 mclk, u32 srate, enum fe_stv0900_demod_num demod) argument
346 stv0900_set_max_symbol_rate(struct stv0900_internal *intp, u32 mclk, u32 srate, enum fe_stv0900_demod_num demod) argument
374 stv0900_set_min_symbol_rate(struct stv0900_internal *intp, u32 mclk, u32 srate, enum fe_stv0900_demod_num demod) argument
1125 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk, enum fe_stv0900_demod_num demod) argument
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H A Dstv6110.c28 u32 mclk; member in struct:stv6110_priv
210 ((((priv->mclk / 1000000) - 16) & 0x1f) << 3);
239 freq = divider * (priv->mclk / 1000);
255 dprintk("%s, freq=%d kHz, mclk=%d Hz\n", __func__,
256 frequency, priv->mclk);
261 ((((priv->mclk / 1000000) - 16) & 0x1f) << 3);
290 p_calc = (priv->mclk / 100000);
295 p_calc_opt = (priv->mclk / 100000);
299 ref = priv->mclk / ((1 << (r_div_opt + 1)) * (1 << (p + 1)));
329 vco_freq = divider * ((priv->mclk / 100
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/linux-master/drivers/clk/hisilicon/
H A Dclk-hi3620.c283 struct clk_mmc *mclk = to_mmc(hw); local
285 if ((req->rate <= 13000000) && (mclk->id == HI3620_MMC_CIUCLK1)) {
322 struct clk_mmc *mclk = to_mmc(hw); local
359 val = readl_relaxed(mclk->clken_reg);
360 val &= ~(1 << mclk->clken_bit);
361 writel_relaxed(val, mclk->clken_reg);
363 val = readl_relaxed(mclk->sam_reg);
364 val = mmc_clk_delay(val, sam, mclk->sam_off, mclk->sam_bits);
365 writel_relaxed(val, mclk
386 struct clk_mmc *mclk = to_mmc(hw); local
413 struct clk_mmc *mclk; local
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/linux-master/sound/soc/intel/skylake/
H A Dskl-i2s.h26 #define get_clk_src(mclk, mask) \
27 ((mclk.mdivctrl & mask) >> SKL_SHIFT(mask))
71 * @mclk: MCLK clock source and divider values
77 struct skl_i2s_config_mclk mclk; member in struct:skl_i2s_config_blob_legacy
85 struct skl_i2s_config_mclk_ext mclk; member in struct:skl_i2s_config_blob_ext
H A Dskl-nhlt.c173 clk_src = get_clk_src(i2s_config->mclk,
176 clk_src = get_clk_src(i2s_config_ext->mclk,
204 static void skl_get_mclk(struct skl_dev *skl, struct skl_ssp_clk *mclk, argument
220 clk_src = get_clk_src(i2s_config->mclk,
222 clkdiv = i2s_config->mclk.mdivr &
225 clk_src = get_clk_src(i2s_config_ext->mclk,
227 clkdiv = i2s_config_ext->mclk.mdivr[0] &
243 mclk[id].rate_cfg[0].rate = parent->rate/div_ratio;
244 mclk[id].rate_cfg[0].config = fmt_cfg;
245 mclk[i
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H A Dskl-ssp-clk.h17 /* xtal/cardinal/pll, parent of ssp clocks and mclk */
19 #define SKL_MAX_SSP_CLK_TYPES 3 /* mclk, sclk, sclkfs */
57 u32 mclk:1; member in struct:skl_dmactrl_mclk_cfg
81 struct skl_dmactrl_mclk_cfg mclk; member in union:skl_clk_ctrl_ipc
92 * rate for mclk will be in rates[0]. For sclk and sclkfs, rates[] store
/linux-master/sound/soc/fsl/
H A Dfsl_rpmsg.h23 * @mclk: master clock for cpu dai (SAI)
36 struct clk *mclk; member in struct:fsl_rpmsg
/linux-master/sound/soc/ti/
H A Ddavinci-evm.c25 struct clk *mclk; member in struct:snd_soc_card_drvdata_davinci
36 if (drvdata->mclk)
37 return clk_prepare_enable(drvdata->mclk);
49 clk_disable_unprepare(drvdata->mclk);
180 struct clk *mclk; local
206 mclk = devm_clk_get(&pdev->dev, "mclk");
207 if (PTR_ERR(mclk) == -EPROBE_DEFER) {
209 } else if (IS_ERR(mclk)) {
210 dev_dbg(&pdev->dev, "mclk no
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/linux-master/sound/soc/mxs/
H A Dmxs-sgtl5000.c25 u32 mclk; local
31 mclk = 256 * rate;
34 mclk = 512 * rate;
39 ret = snd_soc_dai_set_sysclk(codec_dai, SGTL5000_SYSCLK, mclk, 0);
42 mclk / 1000000, mclk / 1000 % 1000);
47 ret = snd_soc_dai_set_sysclk(cpu_dai, MXS_SAIF_MCLK, mclk, 0);
50 mclk / 1000000, mclk / 1000 % 1000);
141 * The Sgtl5000 sysclk is derived from saif0 mclk an
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H A Dmxs-saif.h103 unsigned int mclk; member in struct:mxs_saif
121 extern int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
/linux-master/include/sound/
H A Dwm8962.h37 struct clk *mclk; member in struct:wm8962_pdata
/linux-master/drivers/gpu/drm/radeon/
H A Drv730_dpm.c118 LPRV7XX_SMC_MCLK_VALUE mclk)
183 mclk->mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
184 mclk->mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl);
185 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock);
186 mclk->mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
187 mclk->mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2);
188 mclk->mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3);
189 mclk->mclk730.vMPLL_SS = cpu_to_be32(mpll_ss);
190 mclk->mclk730.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
294 table->ACPIState.levels[0].mclk
116 rv730_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, LPRV7XX_SMC_MCLK_VALUE mclk) argument
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H A Drv740_dpm.c187 RV7XX_SMC_MCLK_VALUE *mclk)
274 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock);
275 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
276 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
277 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
278 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
279 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
280 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
281 mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1);
282 mclk
185 rv740_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk) argument
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H A Drv770_dpm.c389 RV7XX_SMC_MCLK_VALUE *mclk)
474 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock);
475 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
476 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
477 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
478 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
479 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
480 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
593 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, argument
604 if (mclk <
387 rv770_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk) argument
2182 u32 sclk, mclk; local
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/linux-master/sound/soc/rockchip/
H A Drk3399_gru_sound.c70 unsigned int mclk; local
73 mclk = params_rate(params) * SOUND_FS;
75 ret = snd_soc_dai_set_sysclk(snd_soc_rtd_to_cpu(rtd, 0), 0, mclk, 0);
78 __func__, mclk, ret);
91 unsigned int mclk; local
94 mclk = params_rate(params) * SOUND_FS;
96 ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk,
104 mclk, SND_SOC_CLOCK_IN);
123 int mclk, ret; local
125 /* in bypass mode, the mclk ha
240 unsigned int mclk; local
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H A Drockchip_spdif.c36 struct clk *mclk; member in struct:rk_spdif_dev
72 clk_disable_unprepare(spdif->mclk);
83 ret = clk_prepare_enable(spdif->mclk);
85 dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
91 clk_disable_unprepare(spdif->mclk);
101 clk_disable_unprepare(spdif->mclk);
114 int srate, mclk; local
118 mclk = srate * 128;
135 ret = clk_set_rate(spdif->mclk, mclk);
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/linux-master/sound/soc/tegra/
H A Dtegra_wm8903.c36 unsigned int mclk; local
42 mclk = 128 * srate;
45 mclk = 256 * srate;
49 while (mclk < 6000000)
50 mclk *= 2;
52 return mclk;
/linux-master/sound/soc/codecs/
H A Dwm8731.c229 u32 mclk; member in struct:_coeff_div
237 /* codec mclk clock divider coefficients */
302 static inline int get_coeff(int mclk, int rate) argument
307 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
371 if (wm8731->mclk && clk_set_rate(wm8731->mclk, freq))
473 if (wm8731->mclk) {
474 ret = clk_prepare_enable(wm8731->mclk);
496 if (wm8731->mclk)
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H A Dwm8731.h48 struct clk *mclk; member in struct:wm8731_priv
/linux-master/sound/soc/intel/boards/
H A Dcht_bsw_rt5672.c34 struct clk *mclk; member in struct:cht_mc_private
66 if (ctx->mclk) {
67 ret = clk_prepare_enable(ctx->mclk);
103 if (ctx->mclk)
104 clk_disable_unprepare(ctx->mclk);
242 if (ctx->mclk) {
253 ret = clk_prepare_enable(ctx->mclk);
255 clk_disable_unprepare(ctx->mclk);
257 ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ);
502 drv->mclk
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H A Dcht_bsw_max98090_ti.c36 struct clk *mclk; member in struct:cht_mc_private
62 ret = clk_prepare_enable(ctx->mclk);
69 clk_disable_unprepare(ctx->mclk);
239 ret = clk_prepare_enable(ctx->mclk);
241 clk_disable_unprepare(ctx->mclk);
243 ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ);
578 drv->mclk = devm_clk_get(dev, mclk_name);
579 if (IS_ERR(drv->mclk)) {
582 mclk_name, PTR_ERR(drv->mclk));
583 return PTR_ERR(drv->mclk);
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/linux-master/drivers/iio/adc/
H A Dad7766.c38 struct clk *mclk; member in struct:ad7766
97 ret = clk_prepare_enable(ad7766->mclk);
121 clk_disable_unprepare(ad7766->mclk);
143 *val = clk_get_rate(ad7766->mclk) /
224 ad7766->mclk = devm_clk_get(&spi->dev, "mclk");
225 if (IS_ERR(ad7766->mclk))
226 return PTR_ERR(ad7766->mclk);
/linux-master/sound/soc/cirrus/
H A Dep93xx-i2s.c75 struct clk *mclk; member in struct:ep93xx_i2s_info
115 clk_prepare_enable(info->mclk);
162 clk_disable_unprepare(info->mclk);
344 div = clk_get_rate(info->mclk) / params_rate(params);
354 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
375 return clk_set_rate(info->mclk, freq);
468 info->mclk = clk_get(&pdev->dev, "mclk");
469 if (IS_ERR(info->mclk)) {
470 err = PTR_ERR(info->mclk);
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