Searched refs:hwsp_offset (Results 1 - 12 of 12) sorted by relevance

/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_timeline_types.h49 u32 hwsp_offset; member in struct:intel_timeline
H A Dintel_timeline.c61 u32 ofs = offset_in_page(timeline->hwsp_offset);
86 timeline->hwsp_offset = offset;
97 timeline->hwsp_seqno = (void *)(long)timeline->hwsp_offset;
99 GEM_BUG_ON(timeline->hwsp_offset >= hwsp->size);
208 tl->hwsp_offset =
210 offset_in_page(tl->hwsp_offset);
212 tl->fence_context, tl->hwsp_offset);
311 u32 next_ofs = offset_in_page(tl->hwsp_offset + TIMELINE_SEQNO_BYTES);
317 tl->hwsp_offset = i915_ggtt_offset(tl->hwsp_ggtt) + next_ofs;
353 /* hwsp_offset ma
[all...]
H A Dintel_timeline.h82 u32 *hwsp_offset);
H A Dgen8_engine_cs.c425 static u32 hwsp_offset(const struct i915_request *rq) function
434 return page_mask_bits(tl->hwsp_offset) + offset_in_page(rq->hwsp_seqno);
450 *cs++ = hwsp_offset(rq);
662 return gen8_emit_ggtt_write(cs, rq->fence.seqno, hwsp_offset(rq), 0);
683 hwsp_offset(rq),
704 hwsp_offset(rq),
844 hwsp_offset(rq),
H A Dselftest_timeline.c39 return (address + offset_in_page(tl->hwsp_offset)) / TIMELINE_SEQNO_BYTES;
509 err = emit_ggtt_store_dw(rq, tl->hwsp_offset, value);
586 n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno);
658 n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno);
717 pr_debug("seqno[0]:%08x, hwsp_offset:%08x\n",
718 seqno[0], tl->hwsp_offset);
720 err = emit_ggtt_store_dw(rq, tl->hwsp_offset, seqno[0]);
734 pr_debug("seqno[1]:%08x, hwsp_offset:%08x\n",
735 seqno[1], tl->hwsp_offset);
737 err = emit_ggtt_store_dw(rq, tl->hwsp_offset, seqn
[all...]
H A Dselftest_rc6.c148 *cs++ = ce->timeline->hwsp_offset + 8;
H A Dselftest_engine_cs.c71 *cs++ = tl->hwsp_offset + slot * sizeof(u32);
H A Dintel_engine_cs.c2052 tl ? tl->hwsp_offset : 0,
2333 tl->hwsp_offset);
/linux-master/drivers/gpu/drm/i915/
H A Di915_request.h696 page_mask_bits(i915_request_active_timeline(rq)->hwsp_offset);
700 * Because of wraparound, we cannot simply take tl->hwsp_offset,
702 * offset as for hwsp_offset. Take the top bits from tl->hwsp_offset
H A Di915_request.c1148 u32 hwsp_offset; local
1156 err = intel_timeline_read_hwsp(from, to, &hwsp_offset);
1182 *cs++ = hwsp_offset;
/linux-master/drivers/gpu/drm/i915/selftests/
H A Di915_request.c2009 static u32 hwsp_offset(const struct intel_context *ce, u32 *dw) function
2018 const u32 offset = hwsp_offset(ce, sema);
2093 const u32 offset = hwsp_offset(ce, sema);
2164 const u32 offset = hwsp_offset(ce, sema);
2267 const u32 offset = hwsp_offset(ce, sema);
2358 const u32 offset = hwsp_offset(ce, sema);
2452 const u32 offset = hwsp_offset(ce, sema);
2572 const u32 offset = hwsp_offset(ce, sema);
/linux-master/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_submission.c5711 i915_request_active_timeline(rq)->hwsp_offset,
5787 i915_request_active_timeline(rq)->hwsp_offset,

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