Searched refs:grph (Results 1 - 20 of 20) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_hubbub.c343 output->grph.rgb.max_uncompressed_blk_size = 256;
344 output->grph.rgb.max_compressed_blk_size = 256;
345 output->grph.rgb.independent_64b_blks = false;
346 output->grph.rgb.dcc_controls.dcc_256_256_unconstrained = 1;
347 output->grph.rgb.dcc_controls.dcc_256_128_128 = 1;
350 output->grph.rgb.max_uncompressed_blk_size = 128;
351 output->grph.rgb.max_compressed_blk_size = 128;
352 output->grph.rgb.independent_64b_blks = false;
353 output->grph.rgb.dcc_controls.dcc_128_128_uncontrained = 1;
354 output->grph
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H A Ddcn30_hubp.c103 * base on address->grph.dcc_const_color
108 if (address->grph.addr.quad_part == 0)
115 if (address->grph.meta_addr.quad_part != 0) {
118 address->grph.meta_addr.high_part);
122 address->grph.meta_addr.low_part);
127 address->grph.addr.high_part);
131 address->grph.addr.low_part);
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hubbub.c285 output->grph.rgb.max_uncompressed_blk_size = 256;
286 output->grph.rgb.max_compressed_blk_size = 256;
287 output->grph.rgb.independent_64b_blks = false;
290 output->grph.rgb.max_uncompressed_blk_size = 128;
291 output->grph.rgb.max_compressed_blk_size = 128;
292 output->grph.rgb.independent_64b_blks = false;
295 output->grph.rgb.max_uncompressed_blk_size = 256;
296 output->grph.rgb.max_compressed_blk_size = 64;
297 output->grph.rgb.independent_64b_blks = true;
H A Ddcn20_hubp.c737 * base on address->grph.dcc_const_color
742 if (address->grph.addr.quad_part == 0)
749 if (address->grph.meta_addr.quad_part != 0) {
752 address->grph.meta_addr.high_part);
756 address->grph.meta_addr.low_part);
761 address->grph.addr.high_part);
765 address->grph.addr.low_part);
922 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
925 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
930 if (earliest_inuse_address.grph
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_hubbub.c870 output->grph.rgb.max_uncompressed_blk_size = 256;
871 output->grph.rgb.max_compressed_blk_size = 256;
872 output->grph.rgb.independent_64b_blks = false;
873 output->grph.rgb.dcc_controls.dcc_256_256_unconstrained = 1;
874 output->grph.rgb.dcc_controls.dcc_256_128_128 = 1;
877 output->grph.rgb.max_uncompressed_blk_size = 128;
878 output->grph.rgb.max_compressed_blk_size = 128;
879 output->grph.rgb.independent_64b_blks = false;
880 output->grph.rgb.dcc_controls.dcc_128_128_uncontrained = 1;
881 output->grph
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/linux-master/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn32.c517 REG_WRITE(DMCUB_SCRATCH9, addr->grph.addr.low_part);
518 REG_WRITE(DMCUB_SCRATCH11, addr->grph.meta_addr.low_part);
520 REG_WRITE(DMCUB_SCRATCH12, addr->grph.addr.low_part);
521 REG_WRITE(DMCUB_SCRATCH13, addr->grph.meta_addr.low_part);
527 REG_WRITE(DMCUB_SCRATCH18, addr->grph.addr.low_part);
528 REG_WRITE(DMCUB_SCRATCH19, addr->grph.meta_addr.low_part);
530 REG_WRITE(DMCUB_SCRATCH20, addr->grph.addr.low_part);
531 REG_WRITE(DMCUB_SCRATCH22, addr->grph.meta_addr.low_part);
/linux-master/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_debug.c76 "plane_state->address.grph.addr.quad_part = 0x%llX;\n"
77 "plane_state->address.grph.meta_addr.quad_part = 0x%llX;\n"
85 plane_state->address.grph.addr.quad_part,
86 plane_state->address.grph.meta_addr.quad_part,
193 "flip_addr->address.grph.addr.quad_part = 0x%llX;\n"
194 "flip_addr->address.grph.meta_addr.quad_part = 0x%llX;\n"
197 update->flip_addr->address.grph.addr.quad_part,
198 update->flip_addr->address.grph.meta_addr.quad_part,
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hubbub.c907 output->grph.rgb.max_uncompressed_blk_size = 256;
908 output->grph.rgb.max_compressed_blk_size = 256;
909 output->grph.rgb.independent_64b_blks = false;
912 output->grph.rgb.max_uncompressed_blk_size = 128;
913 output->grph.rgb.max_compressed_blk_size = 128;
914 output->grph.rgb.independent_64b_blks = false;
917 output->grph.rgb.max_uncompressed_blk_size = 256;
918 output->grph.rgb.max_compressed_blk_size = 64;
919 output->grph.rgb.independent_64b_blks = true;
H A Ddcn10_hubp.c383 * base on address->grph.dcc_const_color
388 if (address->grph.addr.quad_part == 0)
395 if (address->grph.meta_addr.quad_part != 0) {
398 address->grph.meta_addr.high_part);
402 address->grph.meta_addr.low_part);
407 address->grph.addr.high_part);
411 address->grph.addr.low_part);
744 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
747 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
752 if (earliest_inuse_address.grph
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_hubp.c709 if (address->grph.addr.quad_part == 0) {
714 if (address->grph.meta_addr.quad_part != 0) {
716 address->grph.meta_addr.low_part;
718 address->grph.meta_addr.high_part;
722 address->grph.addr.low_part;
724 address->grph.addr.high_part;
/linux-master/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_hw_sequencer.c351 pipe_ctx->plane_state->address.grph.addr.high_part,
352 pipe_ctx->plane_state->address.grph.addr.low_part,
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c109 gpu_addr_to_uma(hwseq, &addr->grph.addr);
110 gpu_addr_to_uma(hwseq, &addr->grph.meta_addr);
/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c300 output.grph.rgb.independent_64b_blks != 0)
346 address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
347 address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
792 address->grph.addr.low_part = lower_32_bits(addr);
793 address->grph.addr.high_part = upper_32_bits(addr);
H A Damdgpu_dm.c8517 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8518 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h77 } grph; member in union:dc_plane_address::__anon213
H A Ddc.h322 } grph; member in union:dc_surface_dcc_cap::__anon193
/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_mem_input.c615 DC_ERR("unsupported grph pixel format");
853 if (address->grph.addr.quad_part == 0)
855 program_pri_addr(dce_mi, address->grph.addr);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c929 plane->address.grph.cursor_cache_addr.quad_part;
1036 (plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047;
/linux-master/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_mem_input_v.c138 addr->grph.addr);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c2830 pipe_ctx->plane_state->address.grph.addr.high_part,
2831 pipe_ctx->plane_state->address.grph.addr.low_part,

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