Searched refs:format_revision (Results 1 - 21 of 21) sorted by relevance

/linux-master/drivers/gpu/drm/amd/include/
H A Damdgpu_reg_state.h48 uint8_t format_revision; member in struct:amdgpu_reg_state_header
H A Dkgd_pp_interface.h452 uint8_t format_revision; member in struct:metrics_table_header
H A Datomfirmware.h235 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible member in struct:atom_common_table_header
467 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it.
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Dsmu_v12_0.c331 if (header->format_revision != 3) {
372 smu->smu_table.boot_values.format_revision = header->format_revision;
395 if ((smu->smu_table.boot_values.format_revision == 3) &&
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dppatomfwctrl.c280 uint8_t format_revision, content_revision; local
293 format_revision = ((struct atom_common_table_header *)profile)->format_revision;
296 if (format_revision == 4 && content_revision == 1) {
375 } else if (format_revision == 4 && content_revision == 2) {
604 if ((info->format_revision == 3) && (info->content_revision == 2)) {
608 } else if ((info->format_revision == 3) && (info->content_revision == 1)) {
H A Dvega12_processpptables.c67 PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
366 if (pp_table->sHeader.format_revision >=
H A Dvega10_processpptables.c75 PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
1255 PP_ASSERT_WITH_CODE((pp_table->sHeader.format_revision >=
1309 if (pp_table->sHeader.format_revision >=
H A Dvega20_processpptables.c641 PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
H A Dvega12_hwmgr.c2861 gpu_metrics->common_header.format_revision = 1;
H A Dvega20_hwmgr.c4302 gpu_metrics->common_header.format_revision = 1;
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Daqua_vanjaram.c766 pcie_reg_state->common_header.format_revision = 1;
850 xgmi_reg_state->common_header.format_revision = 1;
923 wafl_reg_state->common_header.format_revision = 1;
1042 usr_reg_state->common_header.format_revision = 1;
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c544 if (header->format_revision != 3) {
585 smu->smu_table.boot_values.format_revision = header->format_revision;
613 if ((smu->smu_table.boot_values.format_revision == 3) &&
H A Darcturus_ppt.c483 smc_dpm_table->table_header.format_revision,
486 if ((smc_dpm_table->table_header.format_revision == 4) &&
H A Dnavi10_ppt.c424 smc_dpm_table->table_header.format_revision,
427 if (smc_dpm_table->table_header.format_revision != 4) {
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0.c553 if (header->format_revision != 3) {
606 smu->smu_table.boot_values.format_revision = header->format_revision;
/linux-master/drivers/gpu/drm/amd/pm/swsmu/
H A Dsmu_cmn.c1028 header->format_revision = frev;
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0.c596 if (header->format_revision != 3) {
649 smu->smu_table.boot_values.format_revision = header->format_revision;
H A Daldebaran_ppt.c425 smc_dpm_table->table_header.format_revision,
428 if ((smc_dpm_table->table_header.format_revision == 4) &&
/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Damdgpu_smu.h300 uint32_t format_revision; member in struct:smu_bios_boot_up_values
/linux-master/drivers/net/ethernet/qlogic/qed/
H A Dqed_mfw_hsi.h2369 u32 format_revision; member in struct:nvm_vpd_image
/linux-master/drivers/gpu/drm/amd/display/dc/bios/
H A Dbios_parser2.c126 (uint32_t) atom_data_tbl->format_revision & 0x3f;
1445 if (!((lvds->table_header.format_revision == 2)

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