1/****************************************************************************\ 2* 3* File Name atomfirmware.h 4* Project This is an interface header file between atombios and OS GPU drivers for SoC15 products 5* 6* Description header file of general definitions for OS and pre-OS video drivers 7* 8* Copyright 2014 Advanced Micro Devices, Inc. 9* 10* Permission is hereby granted, free of charge, to any person obtaining a copy of this software 11* and associated documentation files (the "Software"), to deal in the Software without restriction, 12* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, 13* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, 14* subject to the following conditions: 15* 16* The above copyright notice and this permission notice shall be included in all copies or substantial 17* portions of the Software. 18* 19* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 23* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25* OTHER DEALINGS IN THE SOFTWARE. 26* 27\****************************************************************************/ 28 29/*IMPORTANT NOTES 30* If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file. 31* If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file. 32* If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h. 33*/ 34 35#ifndef _ATOMFIRMWARE_H_ 36#define _ATOMFIRMWARE_H_ 37 38enum atom_bios_header_version_def{ 39 ATOM_MAJOR_VERSION =0x0003, 40 ATOM_MINOR_VERSION =0x0003, 41}; 42 43#ifdef _H2INC 44 #ifndef uint32_t 45 typedef unsigned long uint32_t; 46 #endif 47 48 #ifndef uint16_t 49 typedef unsigned short uint16_t; 50 #endif 51 52 #ifndef uint8_t 53 typedef unsigned char uint8_t; 54 #endif 55#endif 56 57enum atom_crtc_def{ 58 ATOM_CRTC1 =0, 59 ATOM_CRTC2 =1, 60 ATOM_CRTC3 =2, 61 ATOM_CRTC4 =3, 62 ATOM_CRTC5 =4, 63 ATOM_CRTC6 =5, 64 ATOM_CRTC_INVALID =0xff, 65}; 66 67enum atom_ppll_def{ 68 ATOM_PPLL0 =2, 69 ATOM_GCK_DFS =8, 70 ATOM_FCH_CLK =9, 71 ATOM_DP_DTO =11, 72 ATOM_COMBOPHY_PLL0 =20, 73 ATOM_COMBOPHY_PLL1 =21, 74 ATOM_COMBOPHY_PLL2 =22, 75 ATOM_COMBOPHY_PLL3 =23, 76 ATOM_COMBOPHY_PLL4 =24, 77 ATOM_COMBOPHY_PLL5 =25, 78 ATOM_PPLL_INVALID =0xff, 79}; 80 81// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel 82enum atom_dig_def{ 83 ASIC_INT_DIG1_ENCODER_ID =0x03, 84 ASIC_INT_DIG2_ENCODER_ID =0x09, 85 ASIC_INT_DIG3_ENCODER_ID =0x0a, 86 ASIC_INT_DIG4_ENCODER_ID =0x0b, 87 ASIC_INT_DIG5_ENCODER_ID =0x0c, 88 ASIC_INT_DIG6_ENCODER_ID =0x0d, 89 ASIC_INT_DIG7_ENCODER_ID =0x0e, 90}; 91 92//ucEncoderMode 93enum atom_encode_mode_def 94{ 95 ATOM_ENCODER_MODE_DP =0, 96 ATOM_ENCODER_MODE_DP_SST =0, 97 ATOM_ENCODER_MODE_LVDS =1, 98 ATOM_ENCODER_MODE_DVI =2, 99 ATOM_ENCODER_MODE_HDMI =3, 100 ATOM_ENCODER_MODE_DP_AUDIO =5, 101 ATOM_ENCODER_MODE_DP_MST =5, 102 ATOM_ENCODER_MODE_CRT =15, 103 ATOM_ENCODER_MODE_DVO =16, 104}; 105 106enum atom_encoder_refclk_src_def{ 107 ENCODER_REFCLK_SRC_P1PLL =0, 108 ENCODER_REFCLK_SRC_P2PLL =1, 109 ENCODER_REFCLK_SRC_P3PLL =2, 110 ENCODER_REFCLK_SRC_EXTCLK =3, 111 ENCODER_REFCLK_SRC_INVALID =0xff, 112}; 113 114enum atom_scaler_def{ 115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/ 116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication 117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/ 118}; 119 120enum atom_operation_def{ 121 ATOM_DISABLE = 0, 122 ATOM_ENABLE = 1, 123 ATOM_INIT = 7, 124 ATOM_GET_STATUS = 8, 125}; 126 127enum atom_embedded_display_op_def{ 128 ATOM_LCD_BL_OFF = 2, 129 ATOM_LCD_BL_OM = 3, 130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4, 131 ATOM_LCD_SELFTEST_START = 5, 132 ATOM_LCD_SELFTEST_STOP = 6, 133}; 134 135enum atom_spread_spectrum_mode{ 136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01, 137 ATOM_SS_DOWN_SPREAD_MODE = 0x00, 138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01, 139 ATOM_INT_OR_EXT_SS_MASK = 0x02, 140 ATOM_INTERNAL_SS_MASK = 0x00, 141 ATOM_EXTERNAL_SS_MASK = 0x02, 142}; 143 144/* define panel bit per color */ 145enum atom_panel_bit_per_color{ 146 PANEL_BPC_UNDEFINE =0x00, 147 PANEL_6BIT_PER_COLOR =0x01, 148 PANEL_8BIT_PER_COLOR =0x02, 149 PANEL_10BIT_PER_COLOR =0x03, 150 PANEL_12BIT_PER_COLOR =0x04, 151 PANEL_16BIT_PER_COLOR =0x05, 152}; 153 154//ucVoltageType 155enum atom_voltage_type 156{ 157 VOLTAGE_TYPE_VDDC = 1, 158 VOLTAGE_TYPE_MVDDC = 2, 159 VOLTAGE_TYPE_MVDDQ = 3, 160 VOLTAGE_TYPE_VDDCI = 4, 161 VOLTAGE_TYPE_VDDGFX = 5, 162 VOLTAGE_TYPE_PCC = 6, 163 VOLTAGE_TYPE_MVPP = 7, 164 VOLTAGE_TYPE_LEDDPM = 8, 165 VOLTAGE_TYPE_PCC_MVDD = 9, 166 VOLTAGE_TYPE_PCIE_VDDC = 10, 167 VOLTAGE_TYPE_PCIE_VDDR = 11, 168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11, 169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12, 170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13, 171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14, 172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15, 173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16, 174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17, 175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18, 176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19, 177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A, 178}; 179 180enum atom_dgpu_vram_type { 181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50, 182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60, 183 ATOM_DGPU_VRAM_TYPE_HBM2E = 0x61, 184 ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70, 185 ATOM_DGPU_VRAM_TYPE_HBM3 = 0x80, 186}; 187 188enum atom_dp_vs_preemph_def{ 189 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00, 190 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01, 191 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02, 192 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03, 193 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08, 194 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09, 195 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a, 196 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10, 197 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11, 198 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18, 199}; 200 201#define BIOS_ATOM_PREFIX "ATOMBIOS" 202#define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD" 203#define BIOS_STRING_LENGTH 43 204 205/* 206enum atom_string_def{ 207asic_bus_type_pcie_string = "PCI_EXPRESS", 208atom_fire_gl_string = "FGL", 209atom_bios_string = "ATOM" 210}; 211*/ 212 213#pragma pack(1) /* BIOS data must use byte aligment*/ 214 215enum atombios_image_offset{ 216 OFFSET_TO_ATOM_ROM_HEADER_POINTER = 0x00000048, 217 OFFSET_TO_ATOM_ROM_IMAGE_SIZE = 0x00000002, 218 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE = 0x94, 219 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE = 20, /*including the terminator 0x0!*/ 220 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS = 0x2f, 221 OFFSET_TO_GET_ATOMBIOS_STRING_START = 0x6e, 222 OFFSET_TO_VBIOS_PART_NUMBER = 0x80, 223 OFFSET_TO_VBIOS_DATE = 0x50, 224}; 225 226/**************************************************************************** 227* Common header for all tables (Data table, Command function). 228* Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. 229* And the pointer actually points to this header. 230****************************************************************************/ 231 232struct atom_common_table_header 233{ 234 uint16_t structuresize; 235 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible 236 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change 237}; 238 239/**************************************************************************** 240* Structure stores the ROM header. 241****************************************************************************/ 242struct atom_rom_header_v2_2 243{ 244 struct atom_common_table_header table_header; 245 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios, 246 uint16_t bios_segment_address; 247 uint16_t protectedmodeoffset; 248 uint16_t configfilenameoffset; 249 uint16_t crc_block_offset; 250 uint16_t vbios_bootupmessageoffset; 251 uint16_t int10_offset; 252 uint16_t pcibusdevinitcode; 253 uint16_t iobaseaddress; 254 uint16_t subsystem_vendor_id; 255 uint16_t subsystem_id; 256 uint16_t pci_info_offset; 257 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position 258 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position 259 uint16_t reserved; 260 uint32_t pspdirtableoffset; 261}; 262 263/*==============================hw function portion======================================================================*/ 264 265 266/**************************************************************************** 267* Structures used in Command.mtb, each function name is not given here since those function could change from time to time 268* The real functionality of each function is associated with the parameter structure version when defined 269* For all internal cmd function definitions, please reference to atomstruct.h 270****************************************************************************/ 271struct atom_master_list_of_command_functions_v2_1{ 272 uint16_t asic_init; //Function 273 uint16_t cmd_function1; //used as an internal one 274 uint16_t cmd_function2; //used as an internal one 275 uint16_t cmd_function3; //used as an internal one 276 uint16_t digxencodercontrol; //Function 277 uint16_t cmd_function5; //used as an internal one 278 uint16_t cmd_function6; //used as an internal one 279 uint16_t cmd_function7; //used as an internal one 280 uint16_t cmd_function8; //used as an internal one 281 uint16_t cmd_function9; //used as an internal one 282 uint16_t setengineclock; //Function 283 uint16_t setmemoryclock; //Function 284 uint16_t setpixelclock; //Function 285 uint16_t enabledisppowergating; //Function 286 uint16_t cmd_function14; //used as an internal one 287 uint16_t cmd_function15; //used as an internal one 288 uint16_t cmd_function16; //used as an internal one 289 uint16_t cmd_function17; //used as an internal one 290 uint16_t cmd_function18; //used as an internal one 291 uint16_t cmd_function19; //used as an internal one 292 uint16_t cmd_function20; //used as an internal one 293 uint16_t cmd_function21; //used as an internal one 294 uint16_t cmd_function22; //used as an internal one 295 uint16_t cmd_function23; //used as an internal one 296 uint16_t cmd_function24; //used as an internal one 297 uint16_t cmd_function25; //used as an internal one 298 uint16_t cmd_function26; //used as an internal one 299 uint16_t cmd_function27; //used as an internal one 300 uint16_t cmd_function28; //used as an internal one 301 uint16_t cmd_function29; //used as an internal one 302 uint16_t cmd_function30; //used as an internal one 303 uint16_t cmd_function31; //used as an internal one 304 uint16_t cmd_function32; //used as an internal one 305 uint16_t cmd_function33; //used as an internal one 306 uint16_t blankcrtc; //Function 307 uint16_t enablecrtc; //Function 308 uint16_t cmd_function36; //used as an internal one 309 uint16_t cmd_function37; //used as an internal one 310 uint16_t cmd_function38; //used as an internal one 311 uint16_t cmd_function39; //used as an internal one 312 uint16_t cmd_function40; //used as an internal one 313 uint16_t getsmuclockinfo; //Function 314 uint16_t selectcrtc_source; //Function 315 uint16_t cmd_function43; //used as an internal one 316 uint16_t cmd_function44; //used as an internal one 317 uint16_t cmd_function45; //used as an internal one 318 uint16_t setdceclock; //Function 319 uint16_t getmemoryclock; //Function 320 uint16_t getengineclock; //Function 321 uint16_t setcrtc_usingdtdtiming; //Function 322 uint16_t externalencodercontrol; //Function 323 uint16_t cmd_function51; //used as an internal one 324 uint16_t cmd_function52; //used as an internal one 325 uint16_t cmd_function53; //used as an internal one 326 uint16_t processi2cchanneltransaction;//Function 327 uint16_t cmd_function55; //used as an internal one 328 uint16_t cmd_function56; //used as an internal one 329 uint16_t cmd_function57; //used as an internal one 330 uint16_t cmd_function58; //used as an internal one 331 uint16_t cmd_function59; //used as an internal one 332 uint16_t computegpuclockparam; //Function 333 uint16_t cmd_function61; //used as an internal one 334 uint16_t cmd_function62; //used as an internal one 335 uint16_t dynamicmemorysettings; //Function function 336 uint16_t memorytraining; //Function function 337 uint16_t cmd_function65; //used as an internal one 338 uint16_t cmd_function66; //used as an internal one 339 uint16_t setvoltage; //Function 340 uint16_t cmd_function68; //used as an internal one 341 uint16_t readefusevalue; //Function 342 uint16_t cmd_function70; //used as an internal one 343 uint16_t cmd_function71; //used as an internal one 344 uint16_t cmd_function72; //used as an internal one 345 uint16_t cmd_function73; //used as an internal one 346 uint16_t cmd_function74; //used as an internal one 347 uint16_t cmd_function75; //used as an internal one 348 uint16_t dig1transmittercontrol; //Function 349 uint16_t cmd_function77; //used as an internal one 350 uint16_t processauxchanneltransaction;//Function 351 uint16_t cmd_function79; //used as an internal one 352 uint16_t getvoltageinfo; //Function 353}; 354 355struct atom_master_command_function_v2_1 356{ 357 struct atom_common_table_header table_header; 358 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions; 359}; 360 361/**************************************************************************** 362* Structures used in every command function 363****************************************************************************/ 364struct atom_function_attribute 365{ 366 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 367 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 368 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util 369}; 370 371 372/**************************************************************************** 373* Common header for all hw functions. 374* Every function pointed by _master_list_of_hw_function has this common header. 375* And the pointer actually points to this header. 376****************************************************************************/ 377struct atom_rom_hw_function_header 378{ 379 struct atom_common_table_header func_header; 380 struct atom_function_attribute func_attrib; 381}; 382 383 384/*==============================sw data table portion======================================================================*/ 385/**************************************************************************** 386* Structures used in data.mtb, each data table name is not given here since those data table could change from time to time 387* The real name of each table is given when its data structure version is defined 388****************************************************************************/ 389struct atom_master_list_of_data_tables_v2_1{ 390 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/ 391 uint16_t multimedia_info; 392 uint16_t smc_dpm_info; 393 uint16_t sw_datatable3; 394 uint16_t firmwareinfo; /* Shared by various SW components */ 395 uint16_t sw_datatable5; 396 uint16_t lcd_info; /* Shared by various SW components */ 397 uint16_t sw_datatable7; 398 uint16_t smu_info; 399 uint16_t sw_datatable9; 400 uint16_t sw_datatable10; 401 uint16_t vram_usagebyfirmware; /* Shared by various SW components */ 402 uint16_t gpio_pin_lut; /* Shared by various SW components */ 403 uint16_t sw_datatable13; 404 uint16_t gfx_info; 405 uint16_t powerplayinfo; /* Shared by various SW components */ 406 uint16_t sw_datatable16; 407 uint16_t sw_datatable17; 408 uint16_t sw_datatable18; 409 uint16_t sw_datatable19; 410 uint16_t sw_datatable20; 411 uint16_t sw_datatable21; 412 uint16_t displayobjectinfo; /* Shared by various SW components */ 413 uint16_t indirectioaccess; /* used as an internal one */ 414 uint16_t umc_info; /* Shared by various SW components */ 415 uint16_t sw_datatable25; 416 uint16_t sw_datatable26; 417 uint16_t dce_info; /* Shared by various SW components */ 418 uint16_t vram_info; /* Shared by various SW components */ 419 uint16_t sw_datatable29; 420 uint16_t integratedsysteminfo; /* Shared by various SW components */ 421 uint16_t asic_profiling_info; /* Shared by various SW components */ 422 uint16_t voltageobject_info; /* shared by various SW components */ 423 uint16_t sw_datatable33; 424 uint16_t sw_datatable34; 425}; 426 427 428struct atom_master_data_table_v2_1 429{ 430 struct atom_common_table_header table_header; 431 struct atom_master_list_of_data_tables_v2_1 listOfdatatables; 432}; 433 434 435struct atom_dtd_format 436{ 437 uint16_t pixclk; 438 uint16_t h_active; 439 uint16_t h_blanking_time; 440 uint16_t v_active; 441 uint16_t v_blanking_time; 442 uint16_t h_sync_offset; 443 uint16_t h_sync_width; 444 uint16_t v_sync_offset; 445 uint16_t v_syncwidth; 446 uint16_t reserved; 447 uint16_t reserved0; 448 uint8_t h_border; 449 uint8_t v_border; 450 uint16_t miscinfo; 451 uint8_t atom_mode_id; 452 uint8_t refreshrate; 453}; 454 455/* atom_dtd_format.modemiscinfo defintion */ 456enum atom_dtd_format_modemiscinfo{ 457 ATOM_HSYNC_POLARITY = 0x0002, 458 ATOM_VSYNC_POLARITY = 0x0004, 459 ATOM_H_REPLICATIONBY2 = 0x0010, 460 ATOM_V_REPLICATIONBY2 = 0x0020, 461 ATOM_INTERLACE = 0x0080, 462 ATOM_COMPOSITESYNC = 0x0040, 463}; 464 465 466/* utilitypipeline 467 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it. 468 * the location of it can't change 469*/ 470 471 472/* 473 *************************************************************************** 474 Data Table firmwareinfo structure 475 *************************************************************************** 476*/ 477 478struct atom_firmware_info_v3_1 479{ 480 struct atom_common_table_header table_header; 481 uint32_t firmware_revision; 482 uint32_t bootup_sclk_in10khz; 483 uint32_t bootup_mclk_in10khz; 484 uint32_t firmware_capability; // enum atombios_firmware_capability 485 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 486 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 487 uint16_t bootup_vddc_mv; 488 uint16_t bootup_vddci_mv; 489 uint16_t bootup_mvddc_mv; 490 uint16_t bootup_vddgfx_mv; 491 uint8_t mem_module_id; 492 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 493 uint8_t reserved1[2]; 494 uint32_t mc_baseaddr_high; 495 uint32_t mc_baseaddr_low; 496 uint32_t reserved2[6]; 497}; 498 499/* Total 32bit cap indication */ 500enum atombios_firmware_capability 501{ 502 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001, 503 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002, 504 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040, 505 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080, 506 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100, 507 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200, 508 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400, 509 ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000, 510 ATOM_FIRMWARE_CAP_DYNAMIC_BOOT_CFG_ENABLE = 0x0020000, 511}; 512 513enum atom_cooling_solution_id{ 514 AIR_COOLING = 0x00, 515 LIQUID_COOLING = 0x01 516}; 517 518struct atom_firmware_info_v3_2 { 519 struct atom_common_table_header table_header; 520 uint32_t firmware_revision; 521 uint32_t bootup_sclk_in10khz; 522 uint32_t bootup_mclk_in10khz; 523 uint32_t firmware_capability; // enum atombios_firmware_capability 524 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 525 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 526 uint16_t bootup_vddc_mv; 527 uint16_t bootup_vddci_mv; 528 uint16_t bootup_mvddc_mv; 529 uint16_t bootup_vddgfx_mv; 530 uint8_t mem_module_id; 531 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 532 uint8_t reserved1[2]; 533 uint32_t mc_baseaddr_high; 534 uint32_t mc_baseaddr_low; 535 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 536 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 537 uint8_t board_i2c_feature_slave_addr; 538 uint8_t reserved3; 539 uint16_t bootup_mvddq_mv; 540 uint16_t bootup_mvpp_mv; 541 uint32_t zfbstartaddrin16mb; 542 uint32_t reserved2[3]; 543}; 544 545struct atom_firmware_info_v3_3 546{ 547 struct atom_common_table_header table_header; 548 uint32_t firmware_revision; 549 uint32_t bootup_sclk_in10khz; 550 uint32_t bootup_mclk_in10khz; 551 uint32_t firmware_capability; // enum atombios_firmware_capability 552 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 553 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 554 uint16_t bootup_vddc_mv; 555 uint16_t bootup_vddci_mv; 556 uint16_t bootup_mvddc_mv; 557 uint16_t bootup_vddgfx_mv; 558 uint8_t mem_module_id; 559 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 560 uint8_t reserved1[2]; 561 uint32_t mc_baseaddr_high; 562 uint32_t mc_baseaddr_low; 563 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 564 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 565 uint8_t board_i2c_feature_slave_addr; 566 uint8_t reserved3; 567 uint16_t bootup_mvddq_mv; 568 uint16_t bootup_mvpp_mv; 569 uint32_t zfbstartaddrin16mb; 570 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 571 uint32_t reserved2[2]; 572}; 573 574struct atom_firmware_info_v3_4 { 575 struct atom_common_table_header table_header; 576 uint32_t firmware_revision; 577 uint32_t bootup_sclk_in10khz; 578 uint32_t bootup_mclk_in10khz; 579 uint32_t firmware_capability; // enum atombios_firmware_capability 580 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 581 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 582 uint16_t bootup_vddc_mv; 583 uint16_t bootup_vddci_mv; 584 uint16_t bootup_mvddc_mv; 585 uint16_t bootup_vddgfx_mv; 586 uint8_t mem_module_id; 587 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 588 uint8_t reserved1[2]; 589 uint32_t mc_baseaddr_high; 590 uint32_t mc_baseaddr_low; 591 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 592 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 593 uint8_t board_i2c_feature_slave_addr; 594 uint8_t ras_rom_i2c_slave_addr; 595 uint16_t bootup_mvddq_mv; 596 uint16_t bootup_mvpp_mv; 597 uint32_t zfbstartaddrin16mb; 598 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 599 uint32_t mvdd_ratio; // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2) 600 uint16_t hw_bootup_vddgfx_mv; // hw default vddgfx voltage level decide by board strap 601 uint16_t hw_bootup_vddc_mv; // hw default vddc voltage level decide by board strap 602 uint16_t hw_bootup_mvddc_mv; // hw default mvddc voltage level decide by board strap 603 uint16_t hw_bootup_vddci_mv; // hw default vddci voltage level decide by board strap 604 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt 605 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt 606 uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb. 607 uint32_t pspbl_init_done_reg_addr; 608 uint32_t pspbl_init_done_value; 609 uint32_t pspbl_init_done_check_timeout; // time out in unit of us when polling pspbl init done 610 uint32_t reserved[2]; 611}; 612 613struct atom_firmware_info_v3_5 { 614 struct atom_common_table_header table_header; 615 uint32_t firmware_revision; 616 uint32_t bootup_clk_reserved[2]; 617 uint32_t firmware_capability; // enum atombios_firmware_capability 618 uint32_t fw_protect_region_size_in_kb; /* FW allocate a write protect region at top of FB. */ 619 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 620 uint32_t bootup_voltage_reserved[2]; 621 uint8_t mem_module_id; 622 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 623 uint8_t hw_blt_mode; //0:HW_BLT_DMA_PIO_MODE; 1:HW_BLT_LITE_SDMA_MODE; 2:HW_BLT_PCI_IO_MODE 624 uint8_t reserved1; 625 uint32_t mc_baseaddr_high; 626 uint32_t mc_baseaddr_low; 627 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 628 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 629 uint8_t board_i2c_feature_slave_addr; 630 uint8_t ras_rom_i2c_slave_addr; 631 uint32_t bootup_voltage_reserved1; 632 uint32_t zfb_reserved; 633 // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 634 uint32_t pplib_pptable_id; 635 uint32_t hw_voltage_reserved[3]; 636 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt 637 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt 638 uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb. 639 uint32_t pspbl_init_reserved[3]; 640 uint32_t spi_rom_size; // GPU spi rom size 641 uint16_t support_dev_in_objinfo; 642 uint16_t disp_phy_tunning_size; 643 uint32_t reserved[16]; 644}; 645/* 646 *************************************************************************** 647 Data Table lcd_info structure 648 *************************************************************************** 649*/ 650 651struct lcd_info_v2_1 652{ 653 struct atom_common_table_header table_header; 654 struct atom_dtd_format lcd_timing; 655 uint16_t backlight_pwm; 656 uint16_t special_handle_cap; 657 uint16_t panel_misc; 658 uint16_t lvds_max_slink_pclk; 659 uint16_t lvds_ss_percentage; 660 uint16_t lvds_ss_rate_10hz; 661 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/ 662 uint8_t pwr_on_de_to_vary_bl; 663 uint8_t pwr_down_vary_bloff_to_de; 664 uint8_t pwr_down_de_to_digoff; 665 uint8_t pwr_off_delay; 666 uint8_t pwr_on_vary_bl_to_blon; 667 uint8_t pwr_down_bloff_to_vary_bloff; 668 uint8_t panel_bpc; 669 uint8_t dpcd_edp_config_cap; 670 uint8_t dpcd_max_link_rate; 671 uint8_t dpcd_max_lane_count; 672 uint8_t dpcd_max_downspread; 673 uint8_t min_allowed_bl_level; 674 uint8_t max_allowed_bl_level; 675 uint8_t bootup_bl_level; 676 uint8_t dplvdsrxid; 677 uint32_t reserved1[8]; 678}; 679 680/* lcd_info_v2_1.panel_misc defintion */ 681enum atom_lcd_info_panel_misc{ 682 ATOM_PANEL_MISC_FPDI =0x0002, 683}; 684 685//uceDPToLVDSRxId 686enum atom_lcd_info_dptolvds_rx_id 687{ 688 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip 689 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init 690 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init 691}; 692 693 694/* 695 *************************************************************************** 696 Data Table gpio_pin_lut structure 697 *************************************************************************** 698*/ 699 700struct atom_gpio_pin_assignment 701{ 702 uint32_t data_a_reg_index; 703 uint8_t gpio_bitshift; 704 uint8_t gpio_mask_bitshift; 705 uint8_t gpio_id; 706 uint8_t reserved; 707}; 708 709/* atom_gpio_pin_assignment.gpio_id definition */ 710enum atom_gpio_pin_assignment_gpio_id { 711 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */ 712 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */ 713 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */ 714 715 /* gpio_id pre-define id for multiple usage */ 716 /* GPIO use to control PCIE_VDDC in certain SLT board */ 717 PCIE_VDDC_CONTROL_GPIO_PINID = 56, 718 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */ 719 PP_AC_DC_SWITCH_GPIO_PINID = 60, 720 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */ 721 VDDC_VRHOT_GPIO_PINID = 61, 722 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */ 723 VDDC_PCC_GPIO_PINID = 62, 724 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */ 725 EFUSE_CUT_ENABLE_GPIO_PINID = 63, 726 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */ 727 DRAM_SELF_REFRESH_GPIO_PINID = 64, 728 /* Thermal interrupt output->system thermal chip GPIO pin */ 729 THERMAL_INT_OUTPUT_GPIO_PINID =65, 730}; 731 732 733struct atom_gpio_pin_lut_v2_1 734{ 735 struct atom_common_table_header table_header; 736 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */ 737 struct atom_gpio_pin_assignment gpio_pin[8]; 738}; 739 740 741/* 742 * VBIOS/PRE-OS always reserve a FB region at the top of frame buffer. driver should not write 743 * access that region. driver can allocate their own reservation region as long as it does not 744 * overlap firwmare's reservation region. 745 * if (pre-NV1X) atom data table firmwareInfoTable version < 3.3: 746 * in this case, atom data table vram_usagebyfirmwareTable version always <= 2.1 747 * if VBIOS/UEFI GOP is posted: 748 * VBIOS/UEFIGOP update used_by_firmware_in_kb = total reserved size by VBIOS 749 * update start_address_in_kb = total_mem_size_in_kb - used_by_firmware_in_kb; 750 * ( total_mem_size_in_kb = reg(CONFIG_MEMSIZE)<<10) 751 * driver can allocate driver reservation region under firmware reservation, 752 * used_by_driver_in_kb = driver reservation size 753 * driver reservation start address = (start_address_in_kb - used_by_driver_in_kb) 754 * Comment1[hchan]: There is only one reservation at the beginning of the FB reserved by 755 * host driver. Host driver would overwrite the table with the following 756 * used_by_firmware_in_kb = total reserved size for pf-vf info exchange and 757 * set SRIOV_MSG_SHARE_RESERVATION mask start_address_in_kb = 0 758 * else there is no VBIOS reservation region: 759 * driver must allocate driver reservation region at top of FB. 760 * driver set used_by_driver_in_kb = driver reservation size 761 * driver reservation start address = (total_mem_size_in_kb - used_by_driver_in_kb) 762 * same as Comment1 763 * else (NV1X and after): 764 * if VBIOS/UEFI GOP is posted: 765 * VBIOS/UEFIGOP update: 766 * used_by_firmware_in_kb = atom_firmware_Info_v3_3.fw_reserved_size_in_kb; 767 * start_address_in_kb = total_mem_size_in_kb - used_by_firmware_in_kb; 768 * (total_mem_size_in_kb = reg(CONFIG_MEMSIZE)<<10) 769 * if vram_usagebyfirmwareTable version <= 2.1: 770 * driver can allocate driver reservation region under firmware reservation, 771 * driver set used_by_driver_in_kb = driver reservation size 772 * driver reservation start address = start_address_in_kb - used_by_driver_in_kb 773 * same as Comment1 774 * else driver can: 775 * allocate it reservation any place as long as it does overlap pre-OS FW reservation area 776 * set used_by_driver_region0_in_kb = driver reservation size 777 * set driver_region0_start_address_in_kb = driver reservation region start address 778 * Comment2[hchan]: Host driver can set used_by_firmware_in_kb and start_address_in_kb to 779 * zero as the reservation for VF as it doesn���t exist. And Host driver should also 780 * update atom_firmware_Info table to remove the same VBIOS reservation as well. 781 */ 782 783struct vram_usagebyfirmware_v2_1 784{ 785 struct atom_common_table_header table_header; 786 uint32_t start_address_in_kb; 787 uint16_t used_by_firmware_in_kb; 788 uint16_t used_by_driver_in_kb; 789}; 790 791struct vram_usagebyfirmware_v2_2 { 792 struct atom_common_table_header table_header; 793 uint32_t fw_region_start_address_in_kb; 794 uint16_t used_by_firmware_in_kb; 795 uint16_t reserved; 796 uint32_t driver_region0_start_address_in_kb; 797 uint32_t used_by_driver_region0_in_kb; 798 uint32_t reserved32[7]; 799}; 800 801/* 802 *************************************************************************** 803 Data Table displayobjectinfo structure 804 *************************************************************************** 805*/ 806 807enum atom_object_record_type_id { 808 ATOM_I2C_RECORD_TYPE = 1, 809 ATOM_HPD_INT_RECORD_TYPE = 2, 810 ATOM_CONNECTOR_CAP_RECORD_TYPE = 3, 811 ATOM_CONNECTOR_SPEED_UPTO = 4, 812 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE = 9, 813 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE = 16, 814 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE = 17, 815 ATOM_ENCODER_CAP_RECORD_TYPE = 20, 816 ATOM_BRACKET_LAYOUT_RECORD_TYPE = 21, 817 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE = 22, 818 ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE = 23, 819 ATOM_BRACKET_LAYOUT_V2_RECORD_TYPE = 25, 820 ATOM_RECORD_END_TYPE = 0xFF, 821}; 822 823struct atom_common_record_header 824{ 825 uint8_t record_type; //An emun to indicate the record type 826 uint8_t record_size; //The size of the whole record in byte 827}; 828 829struct atom_i2c_record 830{ 831 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE 832 uint8_t i2c_id; 833 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC 834}; 835 836struct atom_hpd_int_record 837{ 838 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE 839 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info 840 uint8_t plugin_pin_state; 841}; 842 843struct atom_connector_caps_record { 844 struct atom_common_record_header 845 record_header; //record_type = ATOM_CONN_CAP_RECORD_TYPE 846 uint16_t connector_caps; //01b if internal display is checked; 10b if internal BL is checked; 0 of Not 847}; 848 849struct atom_connector_speed_record { 850 struct atom_common_record_header 851 record_header; //record_type = ATOM_CONN_SPEED_UPTO 852 uint32_t connector_max_speed; // connector Max speed attribute, it sets 8100 in Mhz when DP connector @8.1Ghz. 853 uint16_t reserved; 854}; 855 856// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap 857enum atom_encoder_caps_def 858{ 859 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN 860 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not. 861 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 862 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. 863 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. 864 ATOM_ENCODER_CAP_RECORD_DP2 =0x10, // DP2 is supported by ASIC/board. 865 ATOM_ENCODER_CAP_RECORD_UHBR10_EN =0x20, // DP2.0 UHBR10 settings is supported by board 866 ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN =0x40, // DP2.0 UHBR13.5 settings is supported by board 867 ATOM_ENCODER_CAP_RECORD_UHBR20_EN =0x80, // DP2.0 UHBR20 settings is supported by board 868 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type. 869}; 870 871struct atom_encoder_caps_record 872{ 873 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE 874 uint32_t encodercaps; 875}; 876 877enum atom_connector_caps_def 878{ 879 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display 880 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq 881}; 882 883struct atom_disp_connector_caps_record 884{ 885 struct atom_common_record_header record_header; 886 uint32_t connectcaps; 887}; 888 889//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 890struct atom_gpio_pin_control_pair 891{ 892 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table 893 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin 894}; 895 896struct atom_object_gpio_cntl_record 897{ 898 struct atom_common_record_header record_header; 899 uint8_t flag; // Future expnadibility 900 uint8_t number_of_pins; // Number of GPIO pins used to control the object 901 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 902}; 903 904//Definitions for GPIO pin state 905enum atom_gpio_pin_control_pinstate_def 906{ 907 GPIO_PIN_TYPE_INPUT = 0x00, 908 GPIO_PIN_TYPE_OUTPUT = 0x10, 909 GPIO_PIN_TYPE_HW_CONTROL = 0x20, 910 911//For GPIO_PIN_TYPE_OUTPUT the following is defined 912 GPIO_PIN_OUTPUT_STATE_MASK = 0x01, 913 GPIO_PIN_OUTPUT_STATE_SHIFT = 0, 914 GPIO_PIN_STATE_ACTIVE_LOW = 0x0, 915 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1, 916}; 917 918// Indexes to GPIO array in GLSync record 919// GLSync record is for Frame Lock/Gen Lock feature. 920enum atom_glsync_record_gpio_index_def 921{ 922 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0, 923 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1, 924 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2, 925 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3, 926 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4, 927 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5, 928 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6, 929 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7, 930 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8, 931 ATOM_GPIO_INDEX_GLSYNC_MAX = 9, 932}; 933 934 935struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 936{ 937 struct atom_common_record_header record_header; 938 uint8_t hpd_pin_map[8]; 939}; 940 941struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 942{ 943 struct atom_common_record_header record_header; 944 uint8_t aux_ddc_map[8]; 945}; 946 947struct atom_connector_forced_tmds_cap_record 948{ 949 struct atom_common_record_header record_header; 950 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 951 uint8_t maxtmdsclkrate_in2_5mhz; 952 uint8_t reserved; 953}; 954 955struct atom_connector_layout_info 956{ 957 uint16_t connectorobjid; 958 uint8_t connector_type; 959 uint8_t position; 960}; 961 962// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 963enum atom_connector_layout_info_connector_type_def 964{ 965 CONNECTOR_TYPE_DVI_D = 1, 966 967 CONNECTOR_TYPE_HDMI = 4, 968 CONNECTOR_TYPE_DISPLAY_PORT = 5, 969 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6, 970}; 971 972struct atom_bracket_layout_record 973{ 974 struct atom_common_record_header record_header; 975 uint8_t bracketlen; 976 uint8_t bracketwidth; 977 uint8_t conn_num; 978 uint8_t reserved; 979 struct atom_connector_layout_info conn_info[1]; 980}; 981struct atom_bracket_layout_record_v2 { 982 struct atom_common_record_header 983 record_header; //record_type = ATOM_BRACKET_LAYOUT_RECORD_TYPE 984 uint8_t bracketlen; //Bracket Length in mm 985 uint8_t bracketwidth; //Bracket Width in mm 986 uint8_t conn_num; //Connector numbering 987 uint8_t mini_type; //Mini Type (0 = Normal; 1 = Mini) 988 uint8_t reserved1; 989 uint8_t reserved2; 990}; 991 992enum atom_connector_layout_info_mini_type_def { 993 MINI_TYPE_NORMAL = 0, 994 MINI_TYPE_MINI = 1, 995}; 996 997enum atom_display_device_tag_def{ 998 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display 999 ATOM_DISPLAY_LCD2_SUPPORT = 0x0020, //second edp device tag 0x0020 for backward compability 1000 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008, 1001 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080, 1002 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200, 1003 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400, 1004 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800, 1005 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040, 1006 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8, 1007}; 1008 1009struct atom_display_object_path_v2 1010{ 1011 uint16_t display_objid; //Connector Object ID or Misc Object ID 1012 uint16_t disp_recordoffset; 1013 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder 1014 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view; 1015 uint16_t encoder_recordoffset; 1016 uint16_t extencoder_recordoffset; 1017 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first 1018 uint8_t priority_id; 1019 uint8_t reserved; 1020}; 1021 1022struct atom_display_object_path_v3 { 1023 uint16_t display_objid; //Connector Object ID or Misc Object ID 1024 uint16_t disp_recordoffset; 1025 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder 1026 uint16_t reserved1; //only on USBC case, otherwise always = 0 1027 uint16_t reserved2; //reserved and always = 0 1028 uint16_t reserved3; //reserved and always = 0 1029 //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, 1030 //a path appears first 1031 uint16_t device_tag; 1032 uint16_t reserved4; //reserved and always = 0 1033}; 1034 1035struct display_object_info_table_v1_4 1036{ 1037 struct atom_common_table_header table_header; 1038 uint16_t supporteddevices; 1039 uint8_t number_of_path; 1040 uint8_t reserved; 1041 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path 1042}; 1043 1044struct display_object_info_table_v1_5 { 1045 struct atom_common_table_header table_header; 1046 uint16_t supporteddevices; 1047 uint8_t number_of_path; 1048 uint8_t reserved; 1049 // the real number of this included in the structure is calculated by using the 1050 // (whole structure size - the header size- number_of_path)/size of atom_display_object_path 1051 struct atom_display_object_path_v3 display_path[8]; 1052}; 1053 1054/* 1055 *************************************************************************** 1056 Data Table dce_info structure 1057 *************************************************************************** 1058*/ 1059struct atom_display_controller_info_v4_1 1060{ 1061 struct atom_common_table_header table_header; 1062 uint32_t display_caps; 1063 uint32_t bootup_dispclk_10khz; 1064 uint16_t dce_refclk_10khz; 1065 uint16_t i2c_engine_refclk_10khz; 1066 uint16_t dvi_ss_percentage; // in unit of 0.001% 1067 uint16_t dvi_ss_rate_10hz; 1068 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1069 uint16_t hdmi_ss_rate_10hz; 1070 uint16_t dp_ss_percentage; // in unit of 0.001% 1071 uint16_t dp_ss_rate_10hz; 1072 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1073 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1074 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1075 uint8_t ss_reserved; 1076 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available 1077 uint8_t reserved1[3]; 1078 uint16_t dpphy_refclk_10khz; 1079 uint16_t reserved2; 1080 uint8_t dceip_min_ver; 1081 uint8_t dceip_max_ver; 1082 uint8_t max_disp_pipe_num; 1083 uint8_t max_vbios_active_disp_pipe_num; 1084 uint8_t max_ppll_num; 1085 uint8_t max_disp_phy_num; 1086 uint8_t max_aux_pairs; 1087 uint8_t remotedisplayconfig; 1088 uint8_t reserved3[8]; 1089}; 1090 1091struct atom_display_controller_info_v4_2 1092{ 1093 struct atom_common_table_header table_header; 1094 uint32_t display_caps; 1095 uint32_t bootup_dispclk_10khz; 1096 uint16_t dce_refclk_10khz; 1097 uint16_t i2c_engine_refclk_10khz; 1098 uint16_t dvi_ss_percentage; // in unit of 0.001% 1099 uint16_t dvi_ss_rate_10hz; 1100 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1101 uint16_t hdmi_ss_rate_10hz; 1102 uint16_t dp_ss_percentage; // in unit of 0.001% 1103 uint16_t dp_ss_rate_10hz; 1104 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1105 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1106 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1107 uint8_t ss_reserved; 1108 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1109 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1110 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1111 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1112 uint16_t dpphy_refclk_10khz; 1113 uint16_t reserved2; 1114 uint8_t dcnip_min_ver; 1115 uint8_t dcnip_max_ver; 1116 uint8_t max_disp_pipe_num; 1117 uint8_t max_vbios_active_disp_pipe_num; 1118 uint8_t max_ppll_num; 1119 uint8_t max_disp_phy_num; 1120 uint8_t max_aux_pairs; 1121 uint8_t remotedisplayconfig; 1122 uint8_t reserved3[8]; 1123}; 1124 1125struct atom_display_controller_info_v4_3 1126{ 1127 struct atom_common_table_header table_header; 1128 uint32_t display_caps; 1129 uint32_t bootup_dispclk_10khz; 1130 uint16_t dce_refclk_10khz; 1131 uint16_t i2c_engine_refclk_10khz; 1132 uint16_t dvi_ss_percentage; // in unit of 0.001% 1133 uint16_t dvi_ss_rate_10hz; 1134 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1135 uint16_t hdmi_ss_rate_10hz; 1136 uint16_t dp_ss_percentage; // in unit of 0.001% 1137 uint16_t dp_ss_rate_10hz; 1138 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1139 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1140 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1141 uint8_t ss_reserved; 1142 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1143 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1144 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1145 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1146 uint16_t dpphy_refclk_10khz; 1147 uint16_t reserved2; 1148 uint8_t dcnip_min_ver; 1149 uint8_t dcnip_max_ver; 1150 uint8_t max_disp_pipe_num; 1151 uint8_t max_vbios_active_disp_pipe_num; 1152 uint8_t max_ppll_num; 1153 uint8_t max_disp_phy_num; 1154 uint8_t max_aux_pairs; 1155 uint8_t remotedisplayconfig; 1156 uint8_t reserved3[8]; 1157}; 1158 1159struct atom_display_controller_info_v4_4 { 1160 struct atom_common_table_header table_header; 1161 uint32_t display_caps; 1162 uint32_t bootup_dispclk_10khz; 1163 uint16_t dce_refclk_10khz; 1164 uint16_t i2c_engine_refclk_10khz; 1165 uint16_t dvi_ss_percentage; // in unit of 0.001% 1166 uint16_t dvi_ss_rate_10hz; 1167 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1168 uint16_t hdmi_ss_rate_10hz; 1169 uint16_t dp_ss_percentage; // in unit of 0.001% 1170 uint16_t dp_ss_rate_10hz; 1171 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1172 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1173 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1174 uint8_t ss_reserved; 1175 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1176 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1177 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1178 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1179 uint16_t dpphy_refclk_10khz; 1180 uint16_t hw_chip_id; 1181 uint8_t dcnip_min_ver; 1182 uint8_t dcnip_max_ver; 1183 uint8_t max_disp_pipe_num; 1184 uint8_t max_vbios_active_disp_pipum; 1185 uint8_t max_ppll_num; 1186 uint8_t max_disp_phy_num; 1187 uint8_t max_aux_pairs; 1188 uint8_t remotedisplayconfig; 1189 uint32_t dispclk_pll_vco_freq; 1190 uint32_t dp_ref_clk_freq; 1191 uint32_t max_mclk_chg_lat; // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us) 1192 uint32_t max_sr_exit_lat; // Worst case memory self refresh exit time, units of 100ns of ns (0.1us) 1193 uint32_t max_sr_enter_exit_lat; // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us) 1194 uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx 1195 uint16_t dc_golden_table_ver; 1196 uint32_t reserved3[3]; 1197}; 1198 1199struct atom_dc_golden_table_v1 1200{ 1201 uint32_t aux_dphy_rx_control0_val; 1202 uint32_t aux_dphy_tx_control_val; 1203 uint32_t aux_dphy_rx_control1_val; 1204 uint32_t dc_gpio_aux_ctrl_0_val; 1205 uint32_t dc_gpio_aux_ctrl_1_val; 1206 uint32_t dc_gpio_aux_ctrl_2_val; 1207 uint32_t dc_gpio_aux_ctrl_3_val; 1208 uint32_t dc_gpio_aux_ctrl_4_val; 1209 uint32_t dc_gpio_aux_ctrl_5_val; 1210 uint32_t reserved[23]; 1211}; 1212 1213enum dce_info_caps_def { 1214 // only for VBIOS 1215 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED = 0x02, 1216 // only for VBIOS 1217 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 = 0x04, 1218 // only for VBIOS 1219 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING = 0x08, 1220 // only for VBIOS 1221 DCE_INFO_CAPS_LTTPR_SUPPORT_ENABLE = 0x20, 1222 DCE_INFO_CAPS_VBIOS_LTTPR_TRANSPARENT_ENABLE = 0x40, 1223}; 1224 1225struct atom_display_controller_info_v4_5 1226{ 1227 struct atom_common_table_header table_header; 1228 uint32_t display_caps; 1229 uint32_t bootup_dispclk_10khz; 1230 uint16_t dce_refclk_10khz; 1231 uint16_t i2c_engine_refclk_10khz; 1232 uint16_t dvi_ss_percentage; // in unit of 0.001% 1233 uint16_t dvi_ss_rate_10hz; 1234 uint16_t hdmi_ss_percentage; // in unit of 0.001% 1235 uint16_t hdmi_ss_rate_10hz; 1236 uint16_t dp_ss_percentage; // in unit of 0.001% 1237 uint16_t dp_ss_rate_10hz; 1238 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 1239 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 1240 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 1241 uint8_t ss_reserved; 1242 // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 1243 uint8_t dfp_hardcode_mode_num; 1244 // DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 1245 uint8_t dfp_hardcode_refreshrate; 1246 // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1247 uint8_t vga_hardcode_mode_num; 1248 // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1249 uint8_t vga_hardcode_refreshrate; 1250 uint16_t dpphy_refclk_10khz; 1251 uint16_t hw_chip_id; 1252 uint8_t dcnip_min_ver; 1253 uint8_t dcnip_max_ver; 1254 uint8_t max_disp_pipe_num; 1255 uint8_t max_vbios_active_disp_pipe_num; 1256 uint8_t max_ppll_num; 1257 uint8_t max_disp_phy_num; 1258 uint8_t max_aux_pairs; 1259 uint8_t remotedisplayconfig; 1260 uint32_t dispclk_pll_vco_freq; 1261 uint32_t dp_ref_clk_freq; 1262 // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us) 1263 uint32_t max_mclk_chg_lat; 1264 // Worst case memory self refresh exit time, units of 100ns of ns (0.1us) 1265 uint32_t max_sr_exit_lat; 1266 // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us) 1267 uint32_t max_sr_enter_exit_lat; 1268 uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx 1269 uint16_t dc_golden_table_ver; 1270 uint32_t aux_dphy_rx_control0_val; 1271 uint32_t aux_dphy_tx_control_val; 1272 uint32_t aux_dphy_rx_control1_val; 1273 uint32_t dc_gpio_aux_ctrl_0_val; 1274 uint32_t dc_gpio_aux_ctrl_1_val; 1275 uint32_t dc_gpio_aux_ctrl_2_val; 1276 uint32_t dc_gpio_aux_ctrl_3_val; 1277 uint32_t dc_gpio_aux_ctrl_4_val; 1278 uint32_t dc_gpio_aux_ctrl_5_val; 1279 uint32_t reserved[26]; 1280}; 1281 1282/* 1283 *************************************************************************** 1284 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure 1285 *************************************************************************** 1286*/ 1287struct atom_ext_display_path 1288{ 1289 uint16_t device_tag; //A bit vector to show what devices are supported 1290 uint16_t device_acpi_enum; //16bit device ACPI id. 1291 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions 1292 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT 1293 uint8_t hpdlut_index; //An index into external HPD pin LUT 1294 uint16_t ext_encoder_objid; //external encoder object id 1295 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping 1296 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 1297 uint16_t caps; 1298 uint16_t reserved; 1299}; 1300 1301//usCaps 1302enum ext_display_path_cap_def { 1303 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE = 0x0001, 1304 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN = 0x0002, 1305 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK = 0x007C, 1306 EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 = (0x01 << 2), //PI redriver chip 1307 EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x02 << 2), //TI retimer chip 1308 EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 = (0x03 << 2) //Parade DP->HDMI recoverter chip 1309}; 1310 1311struct atom_external_display_connection_info 1312{ 1313 struct atom_common_table_header table_header; 1314 uint8_t guid[16]; // a GUID is a 16 byte long string 1315 struct atom_ext_display_path path[7]; // total of fixed 7 entries. 1316 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0. 1317 uint8_t stereopinid; // use for eDP panel 1318 uint8_t remotedisplayconfig; 1319 uint8_t edptolvdsrxid; 1320 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value 1321 uint8_t reserved[3]; // for potential expansion 1322}; 1323 1324/* 1325 *************************************************************************** 1326 Data Table integratedsysteminfo structure 1327 *************************************************************************** 1328*/ 1329 1330struct atom_camera_dphy_timing_param 1331{ 1332 uint8_t profile_id; // SENSOR_PROFILES 1333 uint32_t param; 1334}; 1335 1336struct atom_camera_dphy_elec_param 1337{ 1338 uint16_t param[3]; 1339}; 1340 1341struct atom_camera_module_info 1342{ 1343 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user 1344 uint8_t module_name[8]; 1345 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor 1346}; 1347 1348struct atom_camera_flashlight_info 1349{ 1350 uint8_t flashlight_id; // 0: Rear, 1: Front 1351 uint8_t name[8]; 1352}; 1353 1354struct atom_camera_data 1355{ 1356 uint32_t versionCode; 1357 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max 1358 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max 1359 struct atom_camera_dphy_elec_param dphy_param; 1360 uint32_t crc_val; // CRC 1361}; 1362 1363 1364struct atom_14nm_dpphy_dvihdmi_tuningset 1365{ 1366 uint32_t max_symclk_in10khz; 1367 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1368 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1369 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1370 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1371 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1372 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms 1373 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL 1374}; 1375 1376struct atom_14nm_dpphy_dp_setting{ 1377 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1378 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1379 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1380 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1381}; 1382 1383struct atom_14nm_dpphy_dp_tuningset{ 1384 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1385 uint8_t version; 1386 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset 1387 uint16_t reserved; 1388 struct atom_14nm_dpphy_dp_setting dptuning[10]; 1389}; 1390 1391struct atom_14nm_dig_transmitter_info_header_v4_0{ 1392 struct atom_common_table_header table_header; 1393 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl 1394 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl 1395 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl 1396}; 1397 1398struct atom_14nm_combphy_tmds_vs_set 1399{ 1400 uint8_t sym_clk; 1401 uint8_t dig_mode; 1402 uint8_t phy_sel; 1403 uint16_t common_mar_deemph_nom__margin_deemph_val; 1404 uint8_t common_seldeemph60__deemph_6db_4_val; 1405 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ; 1406 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val; 1407 uint8_t margin_deemph_lane0__deemph_sel_val; 1408}; 1409 1410struct atom_DCN_dpphy_dvihdmi_tuningset 1411{ 1412 uint32_t max_symclk_in10khz; 1413 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1414 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1415 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1416 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1417 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1418 uint8_t reserved1; 1419 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1420 uint8_t reserved2; 1421}; 1422 1423struct atom_DCN_dpphy_dp_setting{ 1424 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1425 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1426 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1427 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1428 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1429}; 1430 1431struct atom_DCN_dpphy_dp_tuningset{ 1432 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1433 uint8_t version; 1434 uint16_t table_size; // size of atom_14nm_dpphy_dp_setting 1435 uint16_t reserved; 1436 struct atom_DCN_dpphy_dp_setting dptunings[10]; 1437}; 1438 1439struct atom_i2c_reg_info { 1440 uint8_t ucI2cRegIndex; 1441 uint8_t ucI2cRegVal; 1442}; 1443 1444struct atom_hdmi_retimer_redriver_set { 1445 uint8_t HdmiSlvAddr; 1446 uint8_t HdmiRegNum; 1447 uint8_t Hdmi6GRegNum; 1448 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use 1449 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use. 1450}; 1451 1452struct atom_integrated_system_info_v1_11 1453{ 1454 struct atom_common_table_header table_header; 1455 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1456 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1457 uint32_t system_config; 1458 uint32_t cpucapinfo; 1459 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1460 uint16_t gpuclk_ss_type; 1461 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1462 uint16_t lvds_ss_rate_10hz; 1463 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1464 uint16_t hdmi_ss_rate_10hz; 1465 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1466 uint16_t dvi_ss_rate_10hz; 1467 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1468 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1469 uint16_t backlight_pwm_hz; // pwm frequency in hz 1470 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1471 uint8_t umachannelnumber; // number of memory channels 1472 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */ 1473 uint8_t pwr_on_de_to_vary_bl; 1474 uint8_t pwr_down_vary_bloff_to_de; 1475 uint8_t pwr_down_de_to_digoff; 1476 uint8_t pwr_off_delay; 1477 uint8_t pwr_on_vary_bl_to_blon; 1478 uint8_t pwr_down_bloff_to_vary_bloff; 1479 uint8_t min_allowed_bl_level; 1480 uint8_t htc_hyst_limit; 1481 uint8_t htc_tmp_limit; 1482 uint8_t reserved1; 1483 uint8_t reserved2; 1484 struct atom_external_display_connection_info extdispconninfo; 1485 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset; 1486 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset; 1487 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset; 1488 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set 1489 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set 1490 struct atom_camera_data camera_info; 1491 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1492 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1493 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1494 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1495 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set 1496 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set 1497 struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set 1498 uint32_t reserved[66]; 1499}; 1500 1501struct atom_integrated_system_info_v1_12 1502{ 1503 struct atom_common_table_header table_header; 1504 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1505 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1506 uint32_t system_config; 1507 uint32_t cpucapinfo; 1508 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1509 uint16_t gpuclk_ss_type; 1510 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1511 uint16_t lvds_ss_rate_10hz; 1512 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1513 uint16_t hdmi_ss_rate_10hz; 1514 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1515 uint16_t dvi_ss_rate_10hz; 1516 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1517 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1518 uint16_t backlight_pwm_hz; // pwm frequency in hz 1519 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1520 uint8_t umachannelnumber; // number of memory channels 1521 uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms // 1522 uint8_t pwr_on_de_to_vary_bl; 1523 uint8_t pwr_down_vary_bloff_to_de; 1524 uint8_t pwr_down_de_to_digoff; 1525 uint8_t pwr_off_delay; 1526 uint8_t pwr_on_vary_bl_to_blon; 1527 uint8_t pwr_down_bloff_to_vary_bloff; 1528 uint8_t min_allowed_bl_level; 1529 uint8_t htc_hyst_limit; 1530 uint8_t htc_tmp_limit; 1531 uint8_t reserved1; 1532 uint8_t reserved2; 1533 struct atom_external_display_connection_info extdispconninfo; 1534 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset; 1535 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; 1536 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; 1537 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set 1538 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set 1539 struct atom_camera_data camera_info; 1540 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1541 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1542 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1543 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1544 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set 1545 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set 1546 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set 1547 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset; 1548 uint32_t reserved[63]; 1549}; 1550 1551struct edp_info_table 1552{ 1553 uint16_t edp_backlight_pwm_hz; 1554 uint16_t edp_ss_percentage; 1555 uint16_t edp_ss_rate_10hz; 1556 uint16_t reserved1; 1557 uint32_t reserved2; 1558 uint8_t edp_pwr_on_off_delay; 1559 uint8_t edp_pwr_on_vary_bl_to_blon; 1560 uint8_t edp_pwr_down_bloff_to_vary_bloff; 1561 uint8_t edp_panel_bpc; 1562 uint8_t edp_bootup_bl_level; 1563 uint8_t reserved3[3]; 1564 uint32_t reserved4[3]; 1565}; 1566 1567struct atom_integrated_system_info_v2_1 1568{ 1569 struct atom_common_table_header table_header; 1570 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1571 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1572 uint32_t system_config; 1573 uint32_t cpucapinfo; 1574 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1575 uint16_t gpuclk_ss_type; 1576 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1577 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1578 uint8_t umachannelnumber; // number of memory channels 1579 uint8_t htc_hyst_limit; 1580 uint8_t htc_tmp_limit; 1581 uint8_t reserved1; 1582 uint8_t reserved2; 1583 struct edp_info_table edp1_info; 1584 struct edp_info_table edp2_info; 1585 uint32_t reserved3[8]; 1586 struct atom_external_display_connection_info extdispconninfo; 1587 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset; 1588 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; //add clk6 1589 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset; 1590 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; 1591 uint32_t reserved4[6];//reserve 2*sizeof(atom_DCN_dpphy_dvihdmi_tuningset) 1592 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set 1593 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set 1594 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set 1595 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set 1596 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set 1597 uint32_t reserved5[28];//reserve 2*sizeof(atom_DCN_dpphy_dp_tuningset) 1598 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1599 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1600 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1601 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1602 uint32_t reserved6[30];// reserve size of(atom_camera_data) for camera_info 1603 uint32_t reserved7[32]; 1604 1605}; 1606 1607struct atom_n6_display_phy_tuning_set { 1608 uint8_t display_signal_type; 1609 uint8_t phy_sel; 1610 uint8_t preset_level; 1611 uint8_t reserved1; 1612 uint32_t reserved2; 1613 uint32_t speed_upto; 1614 uint8_t tx_vboost_level; 1615 uint8_t tx_vreg_v2i; 1616 uint8_t tx_vregdrv_byp; 1617 uint8_t tx_term_cntl; 1618 uint8_t tx_peak_level; 1619 uint8_t tx_slew_en; 1620 uint8_t tx_eq_pre; 1621 uint8_t tx_eq_main; 1622 uint8_t tx_eq_post; 1623 uint8_t tx_en_inv_pre; 1624 uint8_t tx_en_inv_post; 1625 uint8_t reserved3; 1626 uint32_t reserved4; 1627 uint32_t reserved5; 1628 uint32_t reserved6; 1629}; 1630 1631struct atom_display_phy_tuning_info { 1632 struct atom_common_table_header table_header; 1633 struct atom_n6_display_phy_tuning_set disp_phy_tuning[1]; 1634}; 1635 1636struct atom_integrated_system_info_v2_2 1637{ 1638 struct atom_common_table_header table_header; 1639 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1640 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1641 uint32_t system_config; 1642 uint32_t cpucapinfo; 1643 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1644 uint16_t gpuclk_ss_type; 1645 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1646 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1647 uint8_t umachannelnumber; // number of memory channels 1648 uint8_t htc_hyst_limit; 1649 uint8_t htc_tmp_limit; 1650 uint8_t reserved1; 1651 uint8_t reserved2; 1652 struct edp_info_table edp1_info; 1653 struct edp_info_table edp2_info; 1654 uint32_t reserved3[8]; 1655 struct atom_external_display_connection_info extdispconninfo; 1656 1657 uint32_t reserved4[189]; 1658}; 1659 1660// system_config 1661enum atom_system_vbiosmisc_def{ 1662 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01, 1663}; 1664 1665 1666// gpucapinfo 1667enum atom_system_gpucapinf_def{ 1668 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10, 1669}; 1670 1671//dpphy_override 1672enum atom_sysinfo_dpphy_override_def{ 1673 ATOM_ENABLE_DVI_TUNINGSET = 0x01, 1674 ATOM_ENABLE_HDMI_TUNINGSET = 0x02, 1675 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04, 1676 ATOM_ENABLE_DP_TUNINGSET = 0x08, 1677 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10, 1678}; 1679 1680//lvds_misc 1681enum atom_sys_info_lvds_misc_def 1682{ 1683 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01, 1684 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04, 1685 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08, 1686}; 1687 1688 1689//memorytype DMI Type 17 offset 12h - Memory Type 1690enum atom_dmi_t17_mem_type_def{ 1691 OtherMemType = 0x01, ///< Assign 01 to Other 1692 UnknownMemType, ///< Assign 02 to Unknown 1693 DramMemType, ///< Assign 03 to DRAM 1694 EdramMemType, ///< Assign 04 to EDRAM 1695 VramMemType, ///< Assign 05 to VRAM 1696 SramMemType, ///< Assign 06 to SRAM 1697 RamMemType, ///< Assign 07 to RAM 1698 RomMemType, ///< Assign 08 to ROM 1699 FlashMemType, ///< Assign 09 to Flash 1700 EepromMemType, ///< Assign 10 to EEPROM 1701 FepromMemType, ///< Assign 11 to FEPROM 1702 EpromMemType, ///< Assign 12 to EPROM 1703 CdramMemType, ///< Assign 13 to CDRAM 1704 ThreeDramMemType, ///< Assign 14 to 3DRAM 1705 SdramMemType, ///< Assign 15 to SDRAM 1706 SgramMemType, ///< Assign 16 to SGRAM 1707 RdramMemType, ///< Assign 17 to RDRAM 1708 DdrMemType, ///< Assign 18 to DDR 1709 Ddr2MemType, ///< Assign 19 to DDR2 1710 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM 1711 Ddr3MemType = 0x18, ///< Assign 24 to DDR3 1712 Fbd2MemType, ///< Assign 25 to FBD2 1713 Ddr4MemType, ///< Assign 26 to DDR4 1714 LpDdrMemType, ///< Assign 27 to LPDDR 1715 LpDdr2MemType, ///< Assign 28 to LPDDR2 1716 LpDdr3MemType, ///< Assign 29 to LPDDR3 1717 LpDdr4MemType, ///< Assign 30 to LPDDR4 1718 GDdr6MemType, ///< Assign 31 to GDDR6 1719 HbmMemType, ///< Assign 32 to HBM 1720 Hbm2MemType, ///< Assign 33 to HBM2 1721 Ddr5MemType, ///< Assign 34 to DDR5 1722 LpDdr5MemType, ///< Assign 35 to LPDDR5 1723}; 1724 1725 1726// this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable 1727struct atom_fusion_system_info_v4 1728{ 1729 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 1730 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable 1731}; 1732 1733 1734/* 1735 *************************************************************************** 1736 Data Table gfx_info structure 1737 *************************************************************************** 1738*/ 1739 1740struct atom_gfx_info_v2_2 1741{ 1742 struct atom_common_table_header table_header; 1743 uint8_t gfxip_min_ver; 1744 uint8_t gfxip_max_ver; 1745 uint8_t max_shader_engines; 1746 uint8_t max_tile_pipes; 1747 uint8_t max_cu_per_sh; 1748 uint8_t max_sh_per_se; 1749 uint8_t max_backends_per_se; 1750 uint8_t max_texture_channel_caches; 1751 uint32_t regaddr_cp_dma_src_addr; 1752 uint32_t regaddr_cp_dma_src_addr_hi; 1753 uint32_t regaddr_cp_dma_dst_addr; 1754 uint32_t regaddr_cp_dma_dst_addr_hi; 1755 uint32_t regaddr_cp_dma_command; 1756 uint32_t regaddr_cp_status; 1757 uint32_t regaddr_rlc_gpu_clock_32; 1758 uint32_t rlc_gpu_timer_refclk; 1759}; 1760 1761struct atom_gfx_info_v2_3 { 1762 struct atom_common_table_header table_header; 1763 uint8_t gfxip_min_ver; 1764 uint8_t gfxip_max_ver; 1765 uint8_t max_shader_engines; 1766 uint8_t max_tile_pipes; 1767 uint8_t max_cu_per_sh; 1768 uint8_t max_sh_per_se; 1769 uint8_t max_backends_per_se; 1770 uint8_t max_texture_channel_caches; 1771 uint32_t regaddr_cp_dma_src_addr; 1772 uint32_t regaddr_cp_dma_src_addr_hi; 1773 uint32_t regaddr_cp_dma_dst_addr; 1774 uint32_t regaddr_cp_dma_dst_addr_hi; 1775 uint32_t regaddr_cp_dma_command; 1776 uint32_t regaddr_cp_status; 1777 uint32_t regaddr_rlc_gpu_clock_32; 1778 uint32_t rlc_gpu_timer_refclk; 1779 uint8_t active_cu_per_sh; 1780 uint8_t active_rb_per_se; 1781 uint16_t gcgoldenoffset; 1782 uint32_t rm21_sram_vmin_value; 1783}; 1784 1785struct atom_gfx_info_v2_4 1786{ 1787 struct atom_common_table_header table_header; 1788 uint8_t gfxip_min_ver; 1789 uint8_t gfxip_max_ver; 1790 uint8_t max_shader_engines; 1791 uint8_t reserved; 1792 uint8_t max_cu_per_sh; 1793 uint8_t max_sh_per_se; 1794 uint8_t max_backends_per_se; 1795 uint8_t max_texture_channel_caches; 1796 uint32_t regaddr_cp_dma_src_addr; 1797 uint32_t regaddr_cp_dma_src_addr_hi; 1798 uint32_t regaddr_cp_dma_dst_addr; 1799 uint32_t regaddr_cp_dma_dst_addr_hi; 1800 uint32_t regaddr_cp_dma_command; 1801 uint32_t regaddr_cp_status; 1802 uint32_t regaddr_rlc_gpu_clock_32; 1803 uint32_t rlc_gpu_timer_refclk; 1804 uint8_t active_cu_per_sh; 1805 uint8_t active_rb_per_se; 1806 uint16_t gcgoldenoffset; 1807 uint16_t gc_num_gprs; 1808 uint16_t gc_gsprim_buff_depth; 1809 uint16_t gc_parameter_cache_depth; 1810 uint16_t gc_wave_size; 1811 uint16_t gc_max_waves_per_simd; 1812 uint16_t gc_lds_size; 1813 uint8_t gc_num_max_gs_thds; 1814 uint8_t gc_gs_table_depth; 1815 uint8_t gc_double_offchip_lds_buffer; 1816 uint8_t gc_max_scratch_slots_per_cu; 1817 uint32_t sram_rm_fuses_val; 1818 uint32_t sram_custom_rm_fuses_val; 1819}; 1820 1821struct atom_gfx_info_v2_7 { 1822 struct atom_common_table_header table_header; 1823 uint8_t gfxip_min_ver; 1824 uint8_t gfxip_max_ver; 1825 uint8_t max_shader_engines; 1826 uint8_t reserved; 1827 uint8_t max_cu_per_sh; 1828 uint8_t max_sh_per_se; 1829 uint8_t max_backends_per_se; 1830 uint8_t max_texture_channel_caches; 1831 uint32_t regaddr_cp_dma_src_addr; 1832 uint32_t regaddr_cp_dma_src_addr_hi; 1833 uint32_t regaddr_cp_dma_dst_addr; 1834 uint32_t regaddr_cp_dma_dst_addr_hi; 1835 uint32_t regaddr_cp_dma_command; 1836 uint32_t regaddr_cp_status; 1837 uint32_t regaddr_rlc_gpu_clock_32; 1838 uint32_t rlc_gpu_timer_refclk; 1839 uint8_t active_cu_per_sh; 1840 uint8_t active_rb_per_se; 1841 uint16_t gcgoldenoffset; 1842 uint16_t gc_num_gprs; 1843 uint16_t gc_gsprim_buff_depth; 1844 uint16_t gc_parameter_cache_depth; 1845 uint16_t gc_wave_size; 1846 uint16_t gc_max_waves_per_simd; 1847 uint16_t gc_lds_size; 1848 uint8_t gc_num_max_gs_thds; 1849 uint8_t gc_gs_table_depth; 1850 uint8_t gc_double_offchip_lds_buffer; 1851 uint8_t gc_max_scratch_slots_per_cu; 1852 uint32_t sram_rm_fuses_val; 1853 uint32_t sram_custom_rm_fuses_val; 1854 uint8_t cut_cu; 1855 uint8_t active_cu_total; 1856 uint8_t cu_reserved[2]; 1857 uint32_t gc_config; 1858 uint8_t inactive_cu_per_se[8]; 1859 uint32_t reserved2[6]; 1860}; 1861 1862struct atom_gfx_info_v3_0 { 1863 struct atom_common_table_header table_header; 1864 uint8_t gfxip_min_ver; 1865 uint8_t gfxip_max_ver; 1866 uint8_t max_shader_engines; 1867 uint8_t max_tile_pipes; 1868 uint8_t max_cu_per_sh; 1869 uint8_t max_sh_per_se; 1870 uint8_t max_backends_per_se; 1871 uint8_t max_texture_channel_caches; 1872 uint32_t regaddr_lsdma_queue0_rb_rptr; 1873 uint32_t regaddr_lsdma_queue0_rb_rptr_hi; 1874 uint32_t regaddr_lsdma_queue0_rb_wptr; 1875 uint32_t regaddr_lsdma_queue0_rb_wptr_hi; 1876 uint32_t regaddr_lsdma_command; 1877 uint32_t regaddr_lsdma_status; 1878 uint32_t regaddr_golden_tsc_count_lower; 1879 uint32_t golden_tsc_count_lower_refclk; 1880 uint8_t active_wgp_per_se; 1881 uint8_t active_rb_per_se; 1882 uint8_t active_se; 1883 uint8_t reserved1; 1884 uint32_t sram_rm_fuses_val; 1885 uint32_t sram_custom_rm_fuses_val; 1886 uint32_t inactive_sa_mask; 1887 uint32_t gc_config; 1888 uint8_t inactive_wgp[16]; 1889 uint8_t inactive_rb[16]; 1890 uint32_t gdfll_as_wait_ctrl_val; 1891 uint32_t gdfll_as_step_ctrl_val; 1892 uint32_t reserved[8]; 1893}; 1894 1895/* 1896 *************************************************************************** 1897 Data Table smu_info structure 1898 *************************************************************************** 1899*/ 1900struct atom_smu_info_v3_1 1901{ 1902 struct atom_common_table_header table_header; 1903 uint8_t smuip_min_ver; 1904 uint8_t smuip_max_ver; 1905 uint8_t smu_rsd1; 1906 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode 1907 uint16_t sclk_ss_percentage; 1908 uint16_t sclk_ss_rate_10hz; 1909 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1910 uint16_t gpuclk_ss_rate_10hz; 1911 uint32_t core_refclk_10khz; 1912 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1913 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1914 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1915 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1916 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1917 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1918 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1919 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1920}; 1921 1922struct atom_smu_info_v3_2 { 1923 struct atom_common_table_header table_header; 1924 uint8_t smuip_min_ver; 1925 uint8_t smuip_max_ver; 1926 uint8_t smu_rsd1; 1927 uint8_t gpuclk_ss_mode; 1928 uint16_t sclk_ss_percentage; 1929 uint16_t sclk_ss_rate_10hz; 1930 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1931 uint16_t gpuclk_ss_rate_10hz; 1932 uint32_t core_refclk_10khz; 1933 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1934 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1935 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1936 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1937 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1938 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1939 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1940 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1941 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1942 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1943 uint16_t smugoldenoffset; 1944 uint32_t gpupll_vco_freq_10khz; 1945 uint32_t bootup_smnclk_10khz; 1946 uint32_t bootup_socclk_10khz; 1947 uint32_t bootup_mp0clk_10khz; 1948 uint32_t bootup_mp1clk_10khz; 1949 uint32_t bootup_lclk_10khz; 1950 uint32_t bootup_dcefclk_10khz; 1951 uint32_t ctf_threshold_override_value; 1952 uint32_t reserved[5]; 1953}; 1954 1955struct atom_smu_info_v3_3 { 1956 struct atom_common_table_header table_header; 1957 uint8_t smuip_min_ver; 1958 uint8_t smuip_max_ver; 1959 uint8_t waflclk_ss_mode; 1960 uint8_t gpuclk_ss_mode; 1961 uint16_t sclk_ss_percentage; 1962 uint16_t sclk_ss_rate_10hz; 1963 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1964 uint16_t gpuclk_ss_rate_10hz; 1965 uint32_t core_refclk_10khz; 1966 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1967 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1968 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1969 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1970 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1971 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1972 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1973 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1974 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1975 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1976 uint16_t smugoldenoffset; 1977 uint32_t gpupll_vco_freq_10khz; 1978 uint32_t bootup_smnclk_10khz; 1979 uint32_t bootup_socclk_10khz; 1980 uint32_t bootup_mp0clk_10khz; 1981 uint32_t bootup_mp1clk_10khz; 1982 uint32_t bootup_lclk_10khz; 1983 uint32_t bootup_dcefclk_10khz; 1984 uint32_t ctf_threshold_override_value; 1985 uint32_t syspll3_0_vco_freq_10khz; 1986 uint32_t syspll3_1_vco_freq_10khz; 1987 uint32_t bootup_fclk_10khz; 1988 uint32_t bootup_waflclk_10khz; 1989 uint32_t smu_info_caps; 1990 uint16_t waflclk_ss_percentage; // in unit of 0.001% 1991 uint16_t smuinitoffset; 1992 uint32_t reserved; 1993}; 1994 1995struct atom_smu_info_v3_5 1996{ 1997 struct atom_common_table_header table_header; 1998 uint8_t smuip_min_ver; 1999 uint8_t smuip_max_ver; 2000 uint8_t waflclk_ss_mode; 2001 uint8_t gpuclk_ss_mode; 2002 uint16_t sclk_ss_percentage; 2003 uint16_t sclk_ss_rate_10hz; 2004 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 2005 uint16_t gpuclk_ss_rate_10hz; 2006 uint32_t core_refclk_10khz; 2007 uint32_t syspll0_1_vco_freq_10khz; 2008 uint32_t syspll0_2_vco_freq_10khz; 2009 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 2010 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 2011 uint16_t smugoldenoffset; 2012 uint32_t syspll0_0_vco_freq_10khz; 2013 uint32_t bootup_smnclk_10khz; 2014 uint32_t bootup_socclk_10khz; 2015 uint32_t bootup_mp0clk_10khz; 2016 uint32_t bootup_mp1clk_10khz; 2017 uint32_t bootup_lclk_10khz; 2018 uint32_t bootup_dcefclk_10khz; 2019 uint32_t ctf_threshold_override_value; 2020 uint32_t syspll3_0_vco_freq_10khz; 2021 uint32_t syspll3_1_vco_freq_10khz; 2022 uint32_t bootup_fclk_10khz; 2023 uint32_t bootup_waflclk_10khz; 2024 uint32_t smu_info_caps; 2025 uint16_t waflclk_ss_percentage; // in unit of 0.001% 2026 uint16_t smuinitoffset; 2027 uint32_t bootup_dprefclk_10khz; 2028 uint32_t bootup_usbclk_10khz; 2029 uint32_t smb_slave_address; 2030 uint32_t cg_fdo_ctrl0_val; 2031 uint32_t cg_fdo_ctrl1_val; 2032 uint32_t cg_fdo_ctrl2_val; 2033 uint32_t gdfll_as_wait_ctrl_val; 2034 uint32_t gdfll_as_step_ctrl_val; 2035 uint32_t bootup_dtbclk_10khz; 2036 uint32_t fclk_syspll_refclk_10khz; 2037 uint32_t smusvi_svc0_val; 2038 uint32_t smusvi_svc1_val; 2039 uint32_t smusvi_svd0_val; 2040 uint32_t smusvi_svd1_val; 2041 uint32_t smusvi_svt0_val; 2042 uint32_t smusvi_svt1_val; 2043 uint32_t cg_tach_ctrl_val; 2044 uint32_t cg_pump_ctrl1_val; 2045 uint32_t cg_pump_tach_ctrl_val; 2046 uint32_t thm_ctf_delay_val; 2047 uint32_t thm_thermal_int_ctrl_val; 2048 uint32_t thm_tmon_config_val; 2049 uint32_t reserved[16]; 2050}; 2051 2052struct atom_smu_info_v3_6 2053{ 2054 struct atom_common_table_header table_header; 2055 uint8_t smuip_min_ver; 2056 uint8_t smuip_max_ver; 2057 uint8_t waflclk_ss_mode; 2058 uint8_t gpuclk_ss_mode; 2059 uint16_t sclk_ss_percentage; 2060 uint16_t sclk_ss_rate_10hz; 2061 uint16_t gpuclk_ss_percentage; 2062 uint16_t gpuclk_ss_rate_10hz; 2063 uint32_t core_refclk_10khz; 2064 uint32_t syspll0_1_vco_freq_10khz; 2065 uint32_t syspll0_2_vco_freq_10khz; 2066 uint8_t pcc_gpio_bit; 2067 uint8_t pcc_gpio_polarity; 2068 uint16_t smugoldenoffset; 2069 uint32_t syspll0_0_vco_freq_10khz; 2070 uint32_t bootup_smnclk_10khz; 2071 uint32_t bootup_socclk_10khz; 2072 uint32_t bootup_mp0clk_10khz; 2073 uint32_t bootup_mp1clk_10khz; 2074 uint32_t bootup_lclk_10khz; 2075 uint32_t bootup_dxioclk_10khz; 2076 uint32_t ctf_threshold_override_value; 2077 uint32_t syspll3_0_vco_freq_10khz; 2078 uint32_t syspll3_1_vco_freq_10khz; 2079 uint32_t bootup_fclk_10khz; 2080 uint32_t bootup_waflclk_10khz; 2081 uint32_t smu_info_caps; 2082 uint16_t waflclk_ss_percentage; 2083 uint16_t smuinitoffset; 2084 uint32_t bootup_gfxavsclk_10khz; 2085 uint32_t bootup_mpioclk_10khz; 2086 uint32_t smb_slave_address; 2087 uint32_t cg_fdo_ctrl0_val; 2088 uint32_t cg_fdo_ctrl1_val; 2089 uint32_t cg_fdo_ctrl2_val; 2090 uint32_t gdfll_as_wait_ctrl_val; 2091 uint32_t gdfll_as_step_ctrl_val; 2092 uint32_t reserved_clk; 2093 uint32_t fclk_syspll_refclk_10khz; 2094 uint32_t smusvi_svc0_val; 2095 uint32_t smusvi_svc1_val; 2096 uint32_t smusvi_svd0_val; 2097 uint32_t smusvi_svd1_val; 2098 uint32_t smusvi_svt0_val; 2099 uint32_t smusvi_svt1_val; 2100 uint32_t cg_tach_ctrl_val; 2101 uint32_t cg_pump_ctrl1_val; 2102 uint32_t cg_pump_tach_ctrl_val; 2103 uint32_t thm_ctf_delay_val; 2104 uint32_t thm_thermal_int_ctrl_val; 2105 uint32_t thm_tmon_config_val; 2106 uint32_t bootup_vclk_10khz; 2107 uint32_t bootup_dclk_10khz; 2108 uint32_t smu_gpiopad_pu_en_val; 2109 uint32_t smu_gpiopad_pd_en_val; 2110 uint32_t reserved[12]; 2111}; 2112 2113struct atom_smu_info_v4_0 { 2114 struct atom_common_table_header table_header; 2115 uint32_t bootup_gfxclk_bypass_10khz; 2116 uint32_t bootup_usrclk_10khz; 2117 uint32_t bootup_csrclk_10khz; 2118 uint32_t core_refclk_10khz; 2119 uint32_t syspll1_vco_freq_10khz; 2120 uint32_t syspll2_vco_freq_10khz; 2121 uint8_t pcc_gpio_bit; 2122 uint8_t pcc_gpio_polarity; 2123 uint16_t bootup_vddusr_mv; 2124 uint32_t syspll0_vco_freq_10khz; 2125 uint32_t bootup_smnclk_10khz; 2126 uint32_t bootup_socclk_10khz; 2127 uint32_t bootup_mp0clk_10khz; 2128 uint32_t bootup_mp1clk_10khz; 2129 uint32_t bootup_lclk_10khz; 2130 uint32_t bootup_dcefclk_10khz; 2131 uint32_t ctf_threshold_override_value; 2132 uint32_t syspll3_vco_freq_10khz; 2133 uint32_t mm_syspll_vco_freq_10khz; 2134 uint32_t bootup_fclk_10khz; 2135 uint32_t bootup_waflclk_10khz; 2136 uint32_t smu_info_caps; 2137 uint16_t waflclk_ss_percentage; 2138 uint16_t smuinitoffset; 2139 uint32_t bootup_dprefclk_10khz; 2140 uint32_t bootup_usbclk_10khz; 2141 uint32_t smb_slave_address; 2142 uint32_t cg_fdo_ctrl0_val; 2143 uint32_t cg_fdo_ctrl1_val; 2144 uint32_t cg_fdo_ctrl2_val; 2145 uint32_t gdfll_as_wait_ctrl_val; 2146 uint32_t gdfll_as_step_ctrl_val; 2147 uint32_t bootup_dtbclk_10khz; 2148 uint32_t fclk_syspll_refclk_10khz; 2149 uint32_t smusvi_svc0_val; 2150 uint32_t smusvi_svc1_val; 2151 uint32_t smusvi_svd0_val; 2152 uint32_t smusvi_svd1_val; 2153 uint32_t smusvi_svt0_val; 2154 uint32_t smusvi_svt1_val; 2155 uint32_t cg_tach_ctrl_val; 2156 uint32_t cg_pump_ctrl1_val; 2157 uint32_t cg_pump_tach_ctrl_val; 2158 uint32_t thm_ctf_delay_val; 2159 uint32_t thm_thermal_int_ctrl_val; 2160 uint32_t thm_tmon_config_val; 2161 uint32_t smbus_timing_cntrl0_val; 2162 uint32_t smbus_timing_cntrl1_val; 2163 uint32_t smbus_timing_cntrl2_val; 2164 uint32_t pwr_disp_timer_global_control_val; 2165 uint32_t bootup_mpioclk_10khz; 2166 uint32_t bootup_dclk0_10khz; 2167 uint32_t bootup_vclk0_10khz; 2168 uint32_t bootup_dclk1_10khz; 2169 uint32_t bootup_vclk1_10khz; 2170 uint32_t bootup_baco400clk_10khz; 2171 uint32_t bootup_baco1200clk_bypass_10khz; 2172 uint32_t bootup_baco700clk_bypass_10khz; 2173 uint32_t reserved[16]; 2174}; 2175 2176/* 2177 *************************************************************************** 2178 Data Table smc_dpm_info structure 2179 *************************************************************************** 2180 */ 2181struct atom_smc_dpm_info_v4_1 2182{ 2183 struct atom_common_table_header table_header; 2184 uint8_t liquid1_i2c_address; 2185 uint8_t liquid2_i2c_address; 2186 uint8_t vr_i2c_address; 2187 uint8_t plx_i2c_address; 2188 2189 uint8_t liquid_i2c_linescl; 2190 uint8_t liquid_i2c_linesda; 2191 uint8_t vr_i2c_linescl; 2192 uint8_t vr_i2c_linesda; 2193 2194 uint8_t plx_i2c_linescl; 2195 uint8_t plx_i2c_linesda; 2196 uint8_t vrsensorpresent; 2197 uint8_t liquidsensorpresent; 2198 2199 uint16_t maxvoltagestepgfx; 2200 uint16_t maxvoltagestepsoc; 2201 2202 uint8_t vddgfxvrmapping; 2203 uint8_t vddsocvrmapping; 2204 uint8_t vddmem0vrmapping; 2205 uint8_t vddmem1vrmapping; 2206 2207 uint8_t gfxulvphasesheddingmask; 2208 uint8_t soculvphasesheddingmask; 2209 uint8_t padding8_v[2]; 2210 2211 uint16_t gfxmaxcurrent; 2212 uint8_t gfxoffset; 2213 uint8_t padding_telemetrygfx; 2214 2215 uint16_t socmaxcurrent; 2216 uint8_t socoffset; 2217 uint8_t padding_telemetrysoc; 2218 2219 uint16_t mem0maxcurrent; 2220 uint8_t mem0offset; 2221 uint8_t padding_telemetrymem0; 2222 2223 uint16_t mem1maxcurrent; 2224 uint8_t mem1offset; 2225 uint8_t padding_telemetrymem1; 2226 2227 uint8_t acdcgpio; 2228 uint8_t acdcpolarity; 2229 uint8_t vr0hotgpio; 2230 uint8_t vr0hotpolarity; 2231 2232 uint8_t vr1hotgpio; 2233 uint8_t vr1hotpolarity; 2234 uint8_t padding1; 2235 uint8_t padding2; 2236 2237 uint8_t ledpin0; 2238 uint8_t ledpin1; 2239 uint8_t ledpin2; 2240 uint8_t padding8_4; 2241 2242 uint8_t pllgfxclkspreadenabled; 2243 uint8_t pllgfxclkspreadpercent; 2244 uint16_t pllgfxclkspreadfreq; 2245 2246 uint8_t uclkspreadenabled; 2247 uint8_t uclkspreadpercent; 2248 uint16_t uclkspreadfreq; 2249 2250 uint8_t socclkspreadenabled; 2251 uint8_t socclkspreadpercent; 2252 uint16_t socclkspreadfreq; 2253 2254 uint8_t acggfxclkspreadenabled; 2255 uint8_t acggfxclkspreadpercent; 2256 uint16_t acggfxclkspreadfreq; 2257 2258 uint8_t Vr2_I2C_address; 2259 uint8_t padding_vr2[3]; 2260 2261 uint32_t boardreserved[9]; 2262}; 2263 2264/* 2265 *************************************************************************** 2266 Data Table smc_dpm_info structure 2267 *************************************************************************** 2268 */ 2269struct atom_smc_dpm_info_v4_3 2270{ 2271 struct atom_common_table_header table_header; 2272 uint8_t liquid1_i2c_address; 2273 uint8_t liquid2_i2c_address; 2274 uint8_t vr_i2c_address; 2275 uint8_t plx_i2c_address; 2276 2277 uint8_t liquid_i2c_linescl; 2278 uint8_t liquid_i2c_linesda; 2279 uint8_t vr_i2c_linescl; 2280 uint8_t vr_i2c_linesda; 2281 2282 uint8_t plx_i2c_linescl; 2283 uint8_t plx_i2c_linesda; 2284 uint8_t vrsensorpresent; 2285 uint8_t liquidsensorpresent; 2286 2287 uint16_t maxvoltagestepgfx; 2288 uint16_t maxvoltagestepsoc; 2289 2290 uint8_t vddgfxvrmapping; 2291 uint8_t vddsocvrmapping; 2292 uint8_t vddmem0vrmapping; 2293 uint8_t vddmem1vrmapping; 2294 2295 uint8_t gfxulvphasesheddingmask; 2296 uint8_t soculvphasesheddingmask; 2297 uint8_t externalsensorpresent; 2298 uint8_t padding8_v; 2299 2300 uint16_t gfxmaxcurrent; 2301 uint8_t gfxoffset; 2302 uint8_t padding_telemetrygfx; 2303 2304 uint16_t socmaxcurrent; 2305 uint8_t socoffset; 2306 uint8_t padding_telemetrysoc; 2307 2308 uint16_t mem0maxcurrent; 2309 uint8_t mem0offset; 2310 uint8_t padding_telemetrymem0; 2311 2312 uint16_t mem1maxcurrent; 2313 uint8_t mem1offset; 2314 uint8_t padding_telemetrymem1; 2315 2316 uint8_t acdcgpio; 2317 uint8_t acdcpolarity; 2318 uint8_t vr0hotgpio; 2319 uint8_t vr0hotpolarity; 2320 2321 uint8_t vr1hotgpio; 2322 uint8_t vr1hotpolarity; 2323 uint8_t padding1; 2324 uint8_t padding2; 2325 2326 uint8_t ledpin0; 2327 uint8_t ledpin1; 2328 uint8_t ledpin2; 2329 uint8_t padding8_4; 2330 2331 uint8_t pllgfxclkspreadenabled; 2332 uint8_t pllgfxclkspreadpercent; 2333 uint16_t pllgfxclkspreadfreq; 2334 2335 uint8_t uclkspreadenabled; 2336 uint8_t uclkspreadpercent; 2337 uint16_t uclkspreadfreq; 2338 2339 uint8_t fclkspreadenabled; 2340 uint8_t fclkspreadpercent; 2341 uint16_t fclkspreadfreq; 2342 2343 uint8_t fllgfxclkspreadenabled; 2344 uint8_t fllgfxclkspreadpercent; 2345 uint16_t fllgfxclkspreadfreq; 2346 2347 uint32_t boardreserved[10]; 2348}; 2349 2350struct smudpm_i2ccontrollerconfig_t { 2351 uint32_t enabled; 2352 uint32_t slaveaddress; 2353 uint32_t controllerport; 2354 uint32_t controllername; 2355 uint32_t thermalthrottler; 2356 uint32_t i2cprotocol; 2357 uint32_t i2cspeed; 2358}; 2359 2360struct atom_smc_dpm_info_v4_4 2361{ 2362 struct atom_common_table_header table_header; 2363 uint32_t i2c_padding[3]; 2364 2365 uint16_t maxvoltagestepgfx; 2366 uint16_t maxvoltagestepsoc; 2367 2368 uint8_t vddgfxvrmapping; 2369 uint8_t vddsocvrmapping; 2370 uint8_t vddmem0vrmapping; 2371 uint8_t vddmem1vrmapping; 2372 2373 uint8_t gfxulvphasesheddingmask; 2374 uint8_t soculvphasesheddingmask; 2375 uint8_t externalsensorpresent; 2376 uint8_t padding8_v; 2377 2378 uint16_t gfxmaxcurrent; 2379 uint8_t gfxoffset; 2380 uint8_t padding_telemetrygfx; 2381 2382 uint16_t socmaxcurrent; 2383 uint8_t socoffset; 2384 uint8_t padding_telemetrysoc; 2385 2386 uint16_t mem0maxcurrent; 2387 uint8_t mem0offset; 2388 uint8_t padding_telemetrymem0; 2389 2390 uint16_t mem1maxcurrent; 2391 uint8_t mem1offset; 2392 uint8_t padding_telemetrymem1; 2393 2394 2395 uint8_t acdcgpio; 2396 uint8_t acdcpolarity; 2397 uint8_t vr0hotgpio; 2398 uint8_t vr0hotpolarity; 2399 2400 uint8_t vr1hotgpio; 2401 uint8_t vr1hotpolarity; 2402 uint8_t padding1; 2403 uint8_t padding2; 2404 2405 2406 uint8_t ledpin0; 2407 uint8_t ledpin1; 2408 uint8_t ledpin2; 2409 uint8_t padding8_4; 2410 2411 2412 uint8_t pllgfxclkspreadenabled; 2413 uint8_t pllgfxclkspreadpercent; 2414 uint16_t pllgfxclkspreadfreq; 2415 2416 2417 uint8_t uclkspreadenabled; 2418 uint8_t uclkspreadpercent; 2419 uint16_t uclkspreadfreq; 2420 2421 2422 uint8_t fclkspreadenabled; 2423 uint8_t fclkspreadpercent; 2424 uint16_t fclkspreadfreq; 2425 2426 2427 uint8_t fllgfxclkspreadenabled; 2428 uint8_t fllgfxclkspreadpercent; 2429 uint16_t fllgfxclkspreadfreq; 2430 2431 2432 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7]; 2433 2434 2435 uint32_t boardreserved[10]; 2436}; 2437 2438enum smudpm_v4_5_i2ccontrollername_e{ 2439 SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0, 2440 SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC, 2441 SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI, 2442 SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD, 2443 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0, 2444 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1, 2445 SMC_V4_5_I2C_CONTROLLER_NAME_PLX, 2446 SMC_V4_5_I2C_CONTROLLER_NAME_SPARE, 2447 SMC_V4_5_I2C_CONTROLLER_NAME_COUNT, 2448}; 2449 2450enum smudpm_v4_5_i2ccontrollerthrottler_e{ 2451 SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 2452 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX, 2453 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC, 2454 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI, 2455 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD, 2456 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0, 2457 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1, 2458 SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX, 2459 SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT, 2460}; 2461 2462enum smudpm_v4_5_i2ccontrollerprotocol_e{ 2463 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0, 2464 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1, 2465 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0, 2466 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1, 2467 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0, 2468 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1, 2469 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT, 2470}; 2471 2472struct smudpm_i2c_controller_config_v2 2473{ 2474 uint8_t Enabled; 2475 uint8_t Speed; 2476 uint8_t Padding[2]; 2477 uint32_t SlaveAddress; 2478 uint8_t ControllerPort; 2479 uint8_t ControllerName; 2480 uint8_t ThermalThrotter; 2481 uint8_t I2cProtocol; 2482}; 2483 2484struct atom_smc_dpm_info_v4_5 2485{ 2486 struct atom_common_table_header table_header; 2487 // SECTION: BOARD PARAMETERS 2488 // I2C Control 2489 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 2490 2491 // SVI2 Board Parameters 2492 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2493 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2494 2495 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2496 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2497 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2498 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2499 2500 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2501 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2502 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 2503 uint8_t Padding8_V; 2504 2505 // Telemetry Settings 2506 uint16_t GfxMaxCurrent; // in Amps 2507 uint8_t GfxOffset; // in Amps 2508 uint8_t Padding_TelemetryGfx; 2509 uint16_t SocMaxCurrent; // in Amps 2510 uint8_t SocOffset; // in Amps 2511 uint8_t Padding_TelemetrySoc; 2512 2513 uint16_t Mem0MaxCurrent; // in Amps 2514 uint8_t Mem0Offset; // in Amps 2515 uint8_t Padding_TelemetryMem0; 2516 2517 uint16_t Mem1MaxCurrent; // in Amps 2518 uint8_t Mem1Offset; // in Amps 2519 uint8_t Padding_TelemetryMem1; 2520 2521 // GPIO Settings 2522 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2523 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2524 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2525 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2526 2527 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2528 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2529 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2530 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2531 2532 // LED Display Settings 2533 uint8_t LedPin0; // GPIO number for LedPin[0] 2534 uint8_t LedPin1; // GPIO number for LedPin[1] 2535 uint8_t LedPin2; // GPIO number for LedPin[2] 2536 uint8_t padding8_4; 2537 2538 // GFXCLK PLL Spread Spectrum 2539 uint8_t PllGfxclkSpreadEnabled; // on or off 2540 uint8_t PllGfxclkSpreadPercent; // Q4.4 2541 uint16_t PllGfxclkSpreadFreq; // kHz 2542 2543 // GFXCLK DFLL Spread Spectrum 2544 uint8_t DfllGfxclkSpreadEnabled; // on or off 2545 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2546 uint16_t DfllGfxclkSpreadFreq; // kHz 2547 2548 // UCLK Spread Spectrum 2549 uint8_t UclkSpreadEnabled; // on or off 2550 uint8_t UclkSpreadPercent; // Q4.4 2551 uint16_t UclkSpreadFreq; // kHz 2552 2553 // SOCCLK Spread Spectrum 2554 uint8_t SoclkSpreadEnabled; // on or off 2555 uint8_t SocclkSpreadPercent; // Q4.4 2556 uint16_t SocclkSpreadFreq; // kHz 2557 2558 // Total board power 2559 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2560 uint16_t BoardPadding; 2561 2562 // Mvdd Svi2 Div Ratio Setting 2563 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 2564 2565 uint32_t BoardReserved[9]; 2566 2567}; 2568 2569struct atom_smc_dpm_info_v4_6 2570{ 2571 struct atom_common_table_header table_header; 2572 // section: board parameters 2573 uint32_t i2c_padding[3]; // old i2c control are moved to new area 2574 2575 uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 2576 uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 2577 2578 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields 2579 uint8_t vddsocvrmapping; // use vr_mapping* bitfields 2580 uint8_t vddmemvrmapping; // use vr_mapping* bitfields 2581 uint8_t boardvrmapping; // use vr_mapping* bitfields 2582 2583 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode 2584 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in) 2585 uint8_t padding8_v[2]; 2586 2587 // telemetry settings 2588 uint16_t gfxmaxcurrent; // in amps 2589 uint8_t gfxoffset; // in amps 2590 uint8_t padding_telemetrygfx; 2591 2592 uint16_t socmaxcurrent; // in amps 2593 uint8_t socoffset; // in amps 2594 uint8_t padding_telemetrysoc; 2595 2596 uint16_t memmaxcurrent; // in amps 2597 uint8_t memoffset; // in amps 2598 uint8_t padding_telemetrymem; 2599 2600 uint16_t boardmaxcurrent; // in amps 2601 uint8_t boardoffset; // in amps 2602 uint8_t padding_telemetryboardinput; 2603 2604 // gpio settings 2605 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event 2606 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event 2607 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event 2608 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event 2609 2610 // gfxclk pll spread spectrum 2611 uint8_t pllgfxclkspreadenabled; // on or off 2612 uint8_t pllgfxclkspreadpercent; // q4.4 2613 uint16_t pllgfxclkspreadfreq; // khz 2614 2615 // uclk spread spectrum 2616 uint8_t uclkspreadenabled; // on or off 2617 uint8_t uclkspreadpercent; // q4.4 2618 uint16_t uclkspreadfreq; // khz 2619 2620 // fclk spread spectrum 2621 uint8_t fclkspreadenabled; // on or off 2622 uint8_t fclkspreadpercent; // q4.4 2623 uint16_t fclkspreadfreq; // khz 2624 2625 2626 // gfxclk fll spread spectrum 2627 uint8_t fllgfxclkspreadenabled; // on or off 2628 uint8_t fllgfxclkspreadpercent; // q4.4 2629 uint16_t fllgfxclkspreadfreq; // khz 2630 2631 // i2c controller structure 2632 struct smudpm_i2c_controller_config_v2 i2ccontrollers[8]; 2633 2634 // memory section 2635 uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask. 2636 2637 uint8_t drambitwidth; // for dram use only. see dram bit width type defines 2638 uint8_t paddingmem[3]; 2639 2640 // total board power 2641 uint16_t totalboardpower; //only needed for tcp estimated case, where tcp = tgp+total board power 2642 uint16_t boardpadding; 2643 2644 // section: xgmi training 2645 uint8_t xgmilinkspeed[4]; 2646 uint8_t xgmilinkwidth[4]; 2647 2648 uint16_t xgmifclkfreq[4]; 2649 uint16_t xgmisocvoltage[4]; 2650 2651 // reserved 2652 uint32_t boardreserved[10]; 2653}; 2654 2655struct atom_smc_dpm_info_v4_7 2656{ 2657 struct atom_common_table_header table_header; 2658 // SECTION: BOARD PARAMETERS 2659 // I2C Control 2660 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 2661 2662 // SVI2 Board Parameters 2663 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2664 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2665 2666 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2667 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2668 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2669 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2670 2671 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2672 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2673 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 2674 uint8_t Padding8_V; 2675 2676 // Telemetry Settings 2677 uint16_t GfxMaxCurrent; // in Amps 2678 uint8_t GfxOffset; // in Amps 2679 uint8_t Padding_TelemetryGfx; 2680 uint16_t SocMaxCurrent; // in Amps 2681 uint8_t SocOffset; // in Amps 2682 uint8_t Padding_TelemetrySoc; 2683 2684 uint16_t Mem0MaxCurrent; // in Amps 2685 uint8_t Mem0Offset; // in Amps 2686 uint8_t Padding_TelemetryMem0; 2687 2688 uint16_t Mem1MaxCurrent; // in Amps 2689 uint8_t Mem1Offset; // in Amps 2690 uint8_t Padding_TelemetryMem1; 2691 2692 // GPIO Settings 2693 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2694 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2695 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2696 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2697 2698 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2699 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2700 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2701 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2702 2703 // LED Display Settings 2704 uint8_t LedPin0; // GPIO number for LedPin[0] 2705 uint8_t LedPin1; // GPIO number for LedPin[1] 2706 uint8_t LedPin2; // GPIO number for LedPin[2] 2707 uint8_t padding8_4; 2708 2709 // GFXCLK PLL Spread Spectrum 2710 uint8_t PllGfxclkSpreadEnabled; // on or off 2711 uint8_t PllGfxclkSpreadPercent; // Q4.4 2712 uint16_t PllGfxclkSpreadFreq; // kHz 2713 2714 // GFXCLK DFLL Spread Spectrum 2715 uint8_t DfllGfxclkSpreadEnabled; // on or off 2716 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2717 uint16_t DfllGfxclkSpreadFreq; // kHz 2718 2719 // UCLK Spread Spectrum 2720 uint8_t UclkSpreadEnabled; // on or off 2721 uint8_t UclkSpreadPercent; // Q4.4 2722 uint16_t UclkSpreadFreq; // kHz 2723 2724 // SOCCLK Spread Spectrum 2725 uint8_t SoclkSpreadEnabled; // on or off 2726 uint8_t SocclkSpreadPercent; // Q4.4 2727 uint16_t SocclkSpreadFreq; // kHz 2728 2729 // Total board power 2730 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2731 uint16_t BoardPadding; 2732 2733 // Mvdd Svi2 Div Ratio Setting 2734 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 2735 2736 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 2737 uint8_t GpioI2cScl; // Serial Clock 2738 uint8_t GpioI2cSda; // Serial Data 2739 uint16_t GpioPadding; 2740 2741 // Additional LED Display Settings 2742 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed 2743 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status 2744 uint16_t LedEnableMask; 2745 2746 // Power Limit Scalars 2747 uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT] 2748 2749 uint8_t MvddUlvPhaseSheddingMask; 2750 uint8_t VddciUlvPhaseSheddingMask; 2751 uint8_t Padding8_Psi1; 2752 uint8_t Padding8_Psi2; 2753 2754 uint32_t BoardReserved[5]; 2755}; 2756 2757struct smudpm_i2c_controller_config_v3 2758{ 2759 uint8_t Enabled; 2760 uint8_t Speed; 2761 uint8_t SlaveAddress; 2762 uint8_t ControllerPort; 2763 uint8_t ControllerName; 2764 uint8_t ThermalThrotter; 2765 uint8_t I2cProtocol; 2766 uint8_t PaddingConfig; 2767}; 2768 2769struct atom_smc_dpm_info_v4_9 2770{ 2771 struct atom_common_table_header table_header; 2772 2773 //SECTION: Gaming Clocks 2774 //uint32_t GamingClk[6]; 2775 2776 // SECTION: I2C Control 2777 struct smudpm_i2c_controller_config_v3 I2cControllers[16]; 2778 2779 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 2780 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 2781 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off 2782 uint8_t I2cSpare; 2783 2784 // SECTION: SVI2 Board Parameters 2785 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2786 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2787 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2788 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2789 2790 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2791 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2792 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2793 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2794 2795 // SECTION: Telemetry Settings 2796 uint16_t GfxMaxCurrent; // in Amps 2797 uint8_t GfxOffset; // in Amps 2798 uint8_t Padding_TelemetryGfx; 2799 2800 uint16_t SocMaxCurrent; // in Amps 2801 uint8_t SocOffset; // in Amps 2802 uint8_t Padding_TelemetrySoc; 2803 2804 uint16_t Mem0MaxCurrent; // in Amps 2805 uint8_t Mem0Offset; // in Amps 2806 uint8_t Padding_TelemetryMem0; 2807 2808 uint16_t Mem1MaxCurrent; // in Amps 2809 uint8_t Mem1Offset; // in Amps 2810 uint8_t Padding_TelemetryMem1; 2811 2812 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 2813 2814 // SECTION: GPIO Settings 2815 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2816 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2817 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2818 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2819 2820 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2821 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2822 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2823 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2824 2825 // LED Display Settings 2826 uint8_t LedPin0; // GPIO number for LedPin[0] 2827 uint8_t LedPin1; // GPIO number for LedPin[1] 2828 uint8_t LedPin2; // GPIO number for LedPin[2] 2829 uint8_t LedEnableMask; 2830 2831 uint8_t LedPcie; // GPIO number for PCIE results 2832 uint8_t LedError; // GPIO number for Error Cases 2833 uint8_t LedSpare1[2]; 2834 2835 // SECTION: Clock Spread Spectrum 2836 2837 // GFXCLK PLL Spread Spectrum 2838 uint8_t PllGfxclkSpreadEnabled; // on or off 2839 uint8_t PllGfxclkSpreadPercent; // Q4.4 2840 uint16_t PllGfxclkSpreadFreq; // kHz 2841 2842 // GFXCLK DFLL Spread Spectrum 2843 uint8_t DfllGfxclkSpreadEnabled; // on or off 2844 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2845 uint16_t DfllGfxclkSpreadFreq; // kHz 2846 2847 // UCLK Spread Spectrum 2848 uint8_t UclkSpreadEnabled; // on or off 2849 uint8_t UclkSpreadPercent; // Q4.4 2850 uint16_t UclkSpreadFreq; // kHz 2851 2852 // FCLK Spread Spectrum 2853 uint8_t FclkSpreadEnabled; // on or off 2854 uint8_t FclkSpreadPercent; // Q4.4 2855 uint16_t FclkSpreadFreq; // kHz 2856 2857 // Section: Memory Config 2858 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 2859 2860 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 2861 uint8_t PaddingMem1[3]; 2862 2863 // Section: Total Board Power 2864 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2865 uint16_t BoardPowerPadding; 2866 2867 // SECTION: XGMI Training 2868 uint8_t XgmiLinkSpeed [4]; 2869 uint8_t XgmiLinkWidth [4]; 2870 2871 uint16_t XgmiFclkFreq [4]; 2872 uint16_t XgmiSocVoltage [4]; 2873 2874 // SECTION: Board Reserved 2875 2876 uint32_t BoardReserved[16]; 2877 2878}; 2879 2880struct atom_smc_dpm_info_v4_10 2881{ 2882 struct atom_common_table_header table_header; 2883 2884 // SECTION: BOARD PARAMETERS 2885 // Telemetry Settings 2886 uint16_t GfxMaxCurrent; // in Amps 2887 uint8_t GfxOffset; // in Amps 2888 uint8_t Padding_TelemetryGfx; 2889 2890 uint16_t SocMaxCurrent; // in Amps 2891 uint8_t SocOffset; // in Amps 2892 uint8_t Padding_TelemetrySoc; 2893 2894 uint16_t MemMaxCurrent; // in Amps 2895 uint8_t MemOffset; // in Amps 2896 uint8_t Padding_TelemetryMem; 2897 2898 uint16_t BoardMaxCurrent; // in Amps 2899 uint8_t BoardOffset; // in Amps 2900 uint8_t Padding_TelemetryBoardInput; 2901 2902 // Platform input telemetry voltage coefficient 2903 uint32_t BoardVoltageCoeffA; // decode by /1000 2904 uint32_t BoardVoltageCoeffB; // decode by /1000 2905 2906 // GPIO Settings 2907 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2908 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2909 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2910 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2911 2912 // UCLK Spread Spectrum 2913 uint8_t UclkSpreadEnabled; // on or off 2914 uint8_t UclkSpreadPercent; // Q4.4 2915 uint16_t UclkSpreadFreq; // kHz 2916 2917 // FCLK Spread Spectrum 2918 uint8_t FclkSpreadEnabled; // on or off 2919 uint8_t FclkSpreadPercent; // Q4.4 2920 uint16_t FclkSpreadFreq; // kHz 2921 2922 // I2C Controller Structure 2923 struct smudpm_i2c_controller_config_v3 I2cControllers[8]; 2924 2925 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 2926 uint8_t GpioI2cScl; // Serial Clock 2927 uint8_t GpioI2cSda; // Serial Data 2928 uint16_t spare5; 2929 2930 uint32_t reserved[16]; 2931}; 2932 2933/* 2934 *************************************************************************** 2935 Data Table asic_profiling_info structure 2936 *************************************************************************** 2937*/ 2938struct atom_asic_profiling_info_v4_1 2939{ 2940 struct atom_common_table_header table_header; 2941 uint32_t maxvddc; 2942 uint32_t minvddc; 2943 uint32_t avfs_meannsigma_acontant0; 2944 uint32_t avfs_meannsigma_acontant1; 2945 uint32_t avfs_meannsigma_acontant2; 2946 uint16_t avfs_meannsigma_dc_tol_sigma; 2947 uint16_t avfs_meannsigma_platform_mean; 2948 uint16_t avfs_meannsigma_platform_sigma; 2949 uint32_t gb_vdroop_table_cksoff_a0; 2950 uint32_t gb_vdroop_table_cksoff_a1; 2951 uint32_t gb_vdroop_table_cksoff_a2; 2952 uint32_t gb_vdroop_table_ckson_a0; 2953 uint32_t gb_vdroop_table_ckson_a1; 2954 uint32_t gb_vdroop_table_ckson_a2; 2955 uint32_t avfsgb_fuse_table_cksoff_m1; 2956 uint32_t avfsgb_fuse_table_cksoff_m2; 2957 uint32_t avfsgb_fuse_table_cksoff_b; 2958 uint32_t avfsgb_fuse_table_ckson_m1; 2959 uint32_t avfsgb_fuse_table_ckson_m2; 2960 uint32_t avfsgb_fuse_table_ckson_b; 2961 uint16_t max_voltage_0_25mv; 2962 uint8_t enable_gb_vdroop_table_cksoff; 2963 uint8_t enable_gb_vdroop_table_ckson; 2964 uint8_t enable_gb_fuse_table_cksoff; 2965 uint8_t enable_gb_fuse_table_ckson; 2966 uint16_t psm_age_comfactor; 2967 uint8_t enable_apply_avfs_cksoff_voltage; 2968 uint8_t reserved; 2969 uint32_t dispclk2gfxclk_a; 2970 uint32_t dispclk2gfxclk_b; 2971 uint32_t dispclk2gfxclk_c; 2972 uint32_t pixclk2gfxclk_a; 2973 uint32_t pixclk2gfxclk_b; 2974 uint32_t pixclk2gfxclk_c; 2975 uint32_t dcefclk2gfxclk_a; 2976 uint32_t dcefclk2gfxclk_b; 2977 uint32_t dcefclk2gfxclk_c; 2978 uint32_t phyclk2gfxclk_a; 2979 uint32_t phyclk2gfxclk_b; 2980 uint32_t phyclk2gfxclk_c; 2981}; 2982 2983struct atom_asic_profiling_info_v4_2 { 2984 struct atom_common_table_header table_header; 2985 uint32_t maxvddc; 2986 uint32_t minvddc; 2987 uint32_t avfs_meannsigma_acontant0; 2988 uint32_t avfs_meannsigma_acontant1; 2989 uint32_t avfs_meannsigma_acontant2; 2990 uint16_t avfs_meannsigma_dc_tol_sigma; 2991 uint16_t avfs_meannsigma_platform_mean; 2992 uint16_t avfs_meannsigma_platform_sigma; 2993 uint32_t gb_vdroop_table_cksoff_a0; 2994 uint32_t gb_vdroop_table_cksoff_a1; 2995 uint32_t gb_vdroop_table_cksoff_a2; 2996 uint32_t gb_vdroop_table_ckson_a0; 2997 uint32_t gb_vdroop_table_ckson_a1; 2998 uint32_t gb_vdroop_table_ckson_a2; 2999 uint32_t avfsgb_fuse_table_cksoff_m1; 3000 uint32_t avfsgb_fuse_table_cksoff_m2; 3001 uint32_t avfsgb_fuse_table_cksoff_b; 3002 uint32_t avfsgb_fuse_table_ckson_m1; 3003 uint32_t avfsgb_fuse_table_ckson_m2; 3004 uint32_t avfsgb_fuse_table_ckson_b; 3005 uint16_t max_voltage_0_25mv; 3006 uint8_t enable_gb_vdroop_table_cksoff; 3007 uint8_t enable_gb_vdroop_table_ckson; 3008 uint8_t enable_gb_fuse_table_cksoff; 3009 uint8_t enable_gb_fuse_table_ckson; 3010 uint16_t psm_age_comfactor; 3011 uint8_t enable_apply_avfs_cksoff_voltage; 3012 uint8_t reserved; 3013 uint32_t dispclk2gfxclk_a; 3014 uint32_t dispclk2gfxclk_b; 3015 uint32_t dispclk2gfxclk_c; 3016 uint32_t pixclk2gfxclk_a; 3017 uint32_t pixclk2gfxclk_b; 3018 uint32_t pixclk2gfxclk_c; 3019 uint32_t dcefclk2gfxclk_a; 3020 uint32_t dcefclk2gfxclk_b; 3021 uint32_t dcefclk2gfxclk_c; 3022 uint32_t phyclk2gfxclk_a; 3023 uint32_t phyclk2gfxclk_b; 3024 uint32_t phyclk2gfxclk_c; 3025 uint32_t acg_gb_vdroop_table_a0; 3026 uint32_t acg_gb_vdroop_table_a1; 3027 uint32_t acg_gb_vdroop_table_a2; 3028 uint32_t acg_avfsgb_fuse_table_m1; 3029 uint32_t acg_avfsgb_fuse_table_m2; 3030 uint32_t acg_avfsgb_fuse_table_b; 3031 uint8_t enable_acg_gb_vdroop_table; 3032 uint8_t enable_acg_gb_fuse_table; 3033 uint32_t acg_dispclk2gfxclk_a; 3034 uint32_t acg_dispclk2gfxclk_b; 3035 uint32_t acg_dispclk2gfxclk_c; 3036 uint32_t acg_pixclk2gfxclk_a; 3037 uint32_t acg_pixclk2gfxclk_b; 3038 uint32_t acg_pixclk2gfxclk_c; 3039 uint32_t acg_dcefclk2gfxclk_a; 3040 uint32_t acg_dcefclk2gfxclk_b; 3041 uint32_t acg_dcefclk2gfxclk_c; 3042 uint32_t acg_phyclk2gfxclk_a; 3043 uint32_t acg_phyclk2gfxclk_b; 3044 uint32_t acg_phyclk2gfxclk_c; 3045}; 3046 3047/* 3048 *************************************************************************** 3049 Data Table multimedia_info structure 3050 *************************************************************************** 3051*/ 3052struct atom_multimedia_info_v2_1 3053{ 3054 struct atom_common_table_header table_header; 3055 uint8_t uvdip_min_ver; 3056 uint8_t uvdip_max_ver; 3057 uint8_t vceip_min_ver; 3058 uint8_t vceip_max_ver; 3059 uint16_t uvd_enc_max_input_width_pixels; 3060 uint16_t uvd_enc_max_input_height_pixels; 3061 uint16_t vce_enc_max_input_width_pixels; 3062 uint16_t vce_enc_max_input_height_pixels; 3063 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 3064 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 3065}; 3066 3067 3068/* 3069 *************************************************************************** 3070 Data Table umc_info structure 3071 *************************************************************************** 3072*/ 3073struct atom_umc_info_v3_1 3074{ 3075 struct atom_common_table_header table_header; 3076 uint32_t ucode_version; 3077 uint32_t ucode_rom_startaddr; 3078 uint32_t ucode_length; 3079 uint16_t umc_reg_init_offset; 3080 uint16_t customer_ucode_name_offset; 3081 uint16_t mclk_ss_percentage; 3082 uint16_t mclk_ss_rate_10hz; 3083 uint8_t umcip_min_ver; 3084 uint8_t umcip_max_ver; 3085 uint8_t vram_type; //enum of atom_dgpu_vram_type 3086 uint8_t umc_config; 3087 uint32_t mem_refclk_10khz; 3088}; 3089 3090// umc_info.umc_config 3091enum atom_umc_config_def { 3092 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001, 3093 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002, 3094 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004, 3095 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008, 3096 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010, 3097 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020, 3098}; 3099 3100struct atom_umc_info_v3_2 3101{ 3102 struct atom_common_table_header table_header; 3103 uint32_t ucode_version; 3104 uint32_t ucode_rom_startaddr; 3105 uint32_t ucode_length; 3106 uint16_t umc_reg_init_offset; 3107 uint16_t customer_ucode_name_offset; 3108 uint16_t mclk_ss_percentage; 3109 uint16_t mclk_ss_rate_10hz; 3110 uint8_t umcip_min_ver; 3111 uint8_t umcip_max_ver; 3112 uint8_t vram_type; //enum of atom_dgpu_vram_type 3113 uint8_t umc_config; 3114 uint32_t mem_refclk_10khz; 3115 uint32_t pstate_uclk_10khz[4]; 3116 uint16_t umcgoldenoffset; 3117 uint16_t densitygoldenoffset; 3118}; 3119 3120struct atom_umc_info_v3_3 3121{ 3122 struct atom_common_table_header table_header; 3123 uint32_t ucode_reserved; 3124 uint32_t ucode_rom_startaddr; 3125 uint32_t ucode_length; 3126 uint16_t umc_reg_init_offset; 3127 uint16_t customer_ucode_name_offset; 3128 uint16_t mclk_ss_percentage; 3129 uint16_t mclk_ss_rate_10hz; 3130 uint8_t umcip_min_ver; 3131 uint8_t umcip_max_ver; 3132 uint8_t vram_type; //enum of atom_dgpu_vram_type 3133 uint8_t umc_config; 3134 uint32_t mem_refclk_10khz; 3135 uint32_t pstate_uclk_10khz[4]; 3136 uint16_t umcgoldenoffset; 3137 uint16_t densitygoldenoffset; 3138 uint32_t umc_config1; 3139 uint32_t bist_data_startaddr; 3140 uint32_t reserved[2]; 3141}; 3142 3143enum atom_umc_config1_def { 3144 UMC_CONFIG1__ENABLE_PSTATE_PHASE_STORE_TRAIN = 0x00000001, 3145 UMC_CONFIG1__ENABLE_AUTO_FRAMING = 0x00000002, 3146 UMC_CONFIG1__ENABLE_RESTORE_BIST_DATA = 0x00000004, 3147 UMC_CONFIG1__DISABLE_STROBE_MODE = 0x00000008, 3148 UMC_CONFIG1__DEBUG_DATA_PARITY_EN = 0x00000010, 3149 UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000, 3150}; 3151 3152struct atom_umc_info_v4_0 { 3153 struct atom_common_table_header table_header; 3154 uint32_t ucode_reserved[5]; 3155 uint8_t umcip_min_ver; 3156 uint8_t umcip_max_ver; 3157 uint8_t vram_type; 3158 uint8_t umc_config; 3159 uint32_t mem_refclk_10khz; 3160 uint32_t clk_reserved[4]; 3161 uint32_t golden_reserved; 3162 uint32_t umc_config1; 3163 uint32_t reserved[2]; 3164 uint8_t channel_num; 3165 uint8_t channel_width; 3166 uint8_t channel_reserve[2]; 3167 uint8_t umc_info_reserved[16]; 3168}; 3169 3170/* 3171 *************************************************************************** 3172 Data Table vram_info structure 3173 *************************************************************************** 3174*/ 3175struct atom_vram_module_v9 { 3176 // Design Specific Values 3177 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 3178 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 3179 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 3180 uint16_t reserved[3]; 3181 uint16_t mem_voltage; // mem_voltage 3182 uint16_t vram_module_size; // Size of atom_vram_module_v9 3183 uint8_t ext_memory_id; // Current memory module ID 3184 uint8_t memory_type; // enum of atom_dgpu_vram_type 3185 uint8_t channel_num; // Number of mem. channels supported in this module 3186 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 3187 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 3188 uint8_t tunningset_id; // MC phy registers set per. 3189 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 3190 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 3191 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id 3192 uint8_t vram_rsd2; // reserved 3193 char dram_pnstring[20]; // part number end with '0'. 3194}; 3195 3196struct atom_vram_info_header_v2_3 { 3197 struct atom_common_table_header table_header; 3198 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 3199 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 3200 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 3201 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 3202 uint16_t dram_data_remap_tbloffset; // reserved for now 3203 uint16_t tmrs_seq_offset; // offset of HBM tmrs 3204 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 3205 uint16_t vram_rsd2; 3206 uint8_t vram_module_num; // indicate number of VRAM module 3207 uint8_t umcip_min_ver; 3208 uint8_t umcip_max_ver; 3209 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 3210 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 3211}; 3212 3213/* 3214 *************************************************************************** 3215 Data Table vram_info v3.0 structure 3216 *************************************************************************** 3217*/ 3218struct atom_vram_module_v3_0 { 3219 uint8_t density; 3220 uint8_t tunningset_id; 3221 uint8_t ext_memory_id; 3222 uint8_t dram_vendor_id; 3223 uint16_t dram_info_offset; 3224 uint16_t mem_tuning_offset; 3225 uint16_t tmrs_seq_offset; 3226 uint16_t reserved1; 3227 uint32_t dram_size_per_ch; 3228 uint32_t reserved[3]; 3229 char dram_pnstring[40]; 3230}; 3231 3232struct atom_vram_info_header_v3_0 { 3233 struct atom_common_table_header table_header; 3234 uint16_t mem_tuning_table_offset; 3235 uint16_t dram_info_table_offset; 3236 uint16_t tmrs_table_offset; 3237 uint16_t mc_init_table_offset; 3238 uint16_t dram_data_remap_table_offset; 3239 uint16_t umc_emuinittable_offset; 3240 uint16_t reserved_sub_table_offset[2]; 3241 uint8_t vram_module_num; 3242 uint8_t umcip_min_ver; 3243 uint8_t umcip_max_ver; 3244 uint8_t mc_phy_tile_num; 3245 uint8_t memory_type; 3246 uint8_t channel_num; 3247 uint8_t channel_width; 3248 uint8_t reserved1; 3249 uint32_t channel_enable; 3250 uint32_t channel1_enable; 3251 uint32_t feature_enable; 3252 uint32_t feature1_enable; 3253 uint32_t hardcode_mem_size; 3254 uint32_t reserved4[4]; 3255 struct atom_vram_module_v3_0 vram_module[8]; 3256}; 3257 3258struct atom_umc_register_addr_info{ 3259 uint32_t umc_register_addr:24; 3260 uint32_t umc_reg_type_ind:1; 3261 uint32_t umc_reg_rsvd:7; 3262}; 3263 3264//atom_umc_register_addr_info. 3265enum atom_umc_register_addr_info_flag{ 3266 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01, 3267}; 3268 3269union atom_umc_register_addr_info_access 3270{ 3271 struct atom_umc_register_addr_info umc_reg_addr; 3272 uint32_t u32umc_reg_addr; 3273}; 3274 3275struct atom_umc_reg_setting_id_config{ 3276 uint32_t memclockrange:24; 3277 uint32_t mem_blk_id:8; 3278}; 3279 3280union atom_umc_reg_setting_id_config_access 3281{ 3282 struct atom_umc_reg_setting_id_config umc_id_access; 3283 uint32_t u32umc_id_access; 3284}; 3285 3286struct atom_umc_reg_setting_data_block{ 3287 union atom_umc_reg_setting_id_config_access block_id; 3288 uint32_t u32umc_reg_data[1]; 3289}; 3290 3291struct atom_umc_init_reg_block{ 3292 uint16_t umc_reg_num; 3293 uint16_t reserved; 3294 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num; 3295 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1]; 3296}; 3297 3298struct atom_vram_module_v10 { 3299 // Design Specific Values 3300 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 3301 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 3302 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 3303 uint16_t reserved[3]; 3304 uint16_t mem_voltage; // mem_voltage 3305 uint16_t vram_module_size; // Size of atom_vram_module_v9 3306 uint8_t ext_memory_id; // Current memory module ID 3307 uint8_t memory_type; // enum of atom_dgpu_vram_type 3308 uint8_t channel_num; // Number of mem. channels supported in this module 3309 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 3310 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 3311 uint8_t tunningset_id; // MC phy registers set per 3312 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 3313 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 3314 uint8_t vram_flags; // bit0= bankgroup enable 3315 uint8_t vram_rsd2; // reserved 3316 uint16_t gddr6_mr10; // gddr6 mode register10 value 3317 uint16_t gddr6_mr1; // gddr6 mode register1 value 3318 uint16_t gddr6_mr2; // gddr6 mode register2 value 3319 uint16_t gddr6_mr7; // gddr6 mode register7 value 3320 char dram_pnstring[20]; // part number end with '0' 3321}; 3322 3323struct atom_vram_info_header_v2_4 { 3324 struct atom_common_table_header table_header; 3325 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 3326 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 3327 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 3328 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 3329 uint16_t dram_data_remap_tbloffset; // reserved for now 3330 uint16_t reserved; // offset of reserved 3331 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 3332 uint16_t vram_rsd2; 3333 uint8_t vram_module_num; // indicate number of VRAM module 3334 uint8_t umcip_min_ver; 3335 uint8_t umcip_max_ver; 3336 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 3337 struct atom_vram_module_v10 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 3338}; 3339 3340struct atom_vram_module_v11 { 3341 // Design Specific Values 3342 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 3343 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 3344 uint16_t mem_voltage; // mem_voltage 3345 uint16_t vram_module_size; // Size of atom_vram_module_v9 3346 uint8_t ext_memory_id; // Current memory module ID 3347 uint8_t memory_type; // enum of atom_dgpu_vram_type 3348 uint8_t channel_num; // Number of mem. channels supported in this module 3349 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 3350 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 3351 uint8_t tunningset_id; // MC phy registers set per. 3352 uint16_t reserved[4]; // reserved 3353 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 3354 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 3355 uint8_t vram_flags; // bit0= bankgroup enable 3356 uint8_t vram_rsd2; // reserved 3357 uint16_t gddr6_mr10; // gddr6 mode register10 value 3358 uint16_t gddr6_mr0; // gddr6 mode register0 value 3359 uint16_t gddr6_mr1; // gddr6 mode register1 value 3360 uint16_t gddr6_mr2; // gddr6 mode register2 value 3361 uint16_t gddr6_mr4; // gddr6 mode register4 value 3362 uint16_t gddr6_mr7; // gddr6 mode register7 value 3363 uint16_t gddr6_mr8; // gddr6 mode register8 value 3364 char dram_pnstring[40]; // part number end with '0'. 3365}; 3366 3367struct atom_gddr6_ac_timing_v2_5 { 3368 uint32_t u32umc_id_access; 3369 uint8_t RL; 3370 uint8_t WL; 3371 uint8_t tRAS; 3372 uint8_t tRC; 3373 3374 uint16_t tREFI; 3375 uint8_t tRFC; 3376 uint8_t tRFCpb; 3377 3378 uint8_t tRREFD; 3379 uint8_t tRCDRD; 3380 uint8_t tRCDWR; 3381 uint8_t tRP; 3382 3383 uint8_t tRRDS; 3384 uint8_t tRRDL; 3385 uint8_t tWR; 3386 uint8_t tWTRS; 3387 3388 uint8_t tWTRL; 3389 uint8_t tFAW; 3390 uint8_t tCCDS; 3391 uint8_t tCCDL; 3392 3393 uint8_t tCRCRL; 3394 uint8_t tCRCWL; 3395 uint8_t tCKE; 3396 uint8_t tCKSRE; 3397 3398 uint8_t tCKSRX; 3399 uint8_t tRTPS; 3400 uint8_t tRTPL; 3401 uint8_t tMRD; 3402 3403 uint8_t tMOD; 3404 uint8_t tXS; 3405 uint8_t tXHP; 3406 uint8_t tXSMRS; 3407 3408 uint32_t tXSH; 3409 3410 uint8_t tPD; 3411 uint8_t tXP; 3412 uint8_t tCPDED; 3413 uint8_t tACTPDE; 3414 3415 uint8_t tPREPDE; 3416 uint8_t tREFPDE; 3417 uint8_t tMRSPDEN; 3418 uint8_t tRDSRE; 3419 3420 uint8_t tWRSRE; 3421 uint8_t tPPD; 3422 uint8_t tCCDMW; 3423 uint8_t tWTRTR; 3424 3425 uint8_t tLTLTR; 3426 uint8_t tREFTR; 3427 uint8_t VNDR; 3428 uint8_t reserved[9]; 3429}; 3430 3431struct atom_gddr6_bit_byte_remap { 3432 uint32_t dphy_byteremap; //mmUMC_DPHY_ByteRemap 3433 uint32_t dphy_bitremap0; //mmUMC_DPHY_BitRemap0 3434 uint32_t dphy_bitremap1; //mmUMC_DPHY_BitRemap1 3435 uint32_t dphy_bitremap2; //mmUMC_DPHY_BitRemap2 3436 uint32_t aphy_bitremap0; //mmUMC_APHY_BitRemap0 3437 uint32_t aphy_bitremap1; //mmUMC_APHY_BitRemap1 3438 uint32_t phy_dram; //mmUMC_PHY_DRAM 3439}; 3440 3441struct atom_gddr6_dram_data_remap { 3442 uint32_t table_size; 3443 uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK 3444 struct atom_gddr6_bit_byte_remap bit_byte_remap[16]; 3445}; 3446 3447struct atom_vram_info_header_v2_5 { 3448 struct atom_common_table_header table_header; 3449 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust settings 3450 uint16_t gddr6_ac_timing_offset; // offset of atom_gddr6_ac_timing_v2_5 structure for memory clock specific UMC settings 3451 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 3452 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 3453 uint16_t dram_data_remap_tbloffset; // offset of atom_gddr6_dram_data_remap array to indicate DRAM data lane to GPU mapping 3454 uint16_t reserved; // offset of reserved 3455 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 3456 uint16_t strobe_mode_patch_tbloffset; // offset of atom_umc_init_reg_block structure for Strobe Mode memory clock specific UMC settings 3457 uint8_t vram_module_num; // indicate number of VRAM module 3458 uint8_t umcip_min_ver; 3459 uint8_t umcip_max_ver; 3460 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 3461 struct atom_vram_module_v11 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 3462}; 3463 3464struct atom_vram_info_header_v2_6 { 3465 struct atom_common_table_header table_header; 3466 uint16_t mem_adjust_tbloffset; 3467 uint16_t mem_clk_patch_tbloffset; 3468 uint16_t mc_adjust_pertile_tbloffset; 3469 uint16_t mc_phyinit_tbloffset; 3470 uint16_t dram_data_remap_tbloffset; 3471 uint16_t tmrs_seq_offset; 3472 uint16_t post_ucode_init_offset; 3473 uint16_t vram_rsd2; 3474 uint8_t vram_module_num; 3475 uint8_t umcip_min_ver; 3476 uint8_t umcip_max_ver; 3477 uint8_t mc_phy_tile_num; 3478 struct atom_vram_module_v9 vram_module[16]; 3479}; 3480/* 3481 *************************************************************************** 3482 Data Table voltageobject_info structure 3483 *************************************************************************** 3484*/ 3485struct atom_i2c_data_entry 3486{ 3487 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit 3488 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit 3489}; 3490 3491struct atom_voltage_object_header_v4{ 3492 uint8_t voltage_type; //enum atom_voltage_type 3493 uint8_t voltage_mode; //enum atom_voltage_object_mode 3494 uint16_t object_size; //Size of Object 3495}; 3496 3497// atom_voltage_object_header_v4.voltage_mode 3498enum atom_voltage_object_mode 3499{ 3500 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4 3501 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4 3502 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4 3503 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4 3504 VOLTAGE_OBJ_EVV = 8, 3505 VOLTAGE_OBJ_MERGED_POWER = 9, 3506}; 3507 3508struct atom_i2c_voltage_object_v4 3509{ 3510 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3511 uint8_t regulator_id; //Indicate Voltage Regulator Id 3512 uint8_t i2c_id; 3513 uint8_t i2c_slave_addr; 3514 uint8_t i2c_control_offset; 3515 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data 3516 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz. 3517 uint8_t reserved[2]; 3518 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff 3519}; 3520 3521// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 3522enum atom_i2c_voltage_control_flag 3523{ 3524 VOLTAGE_DATA_ONE_BYTE = 0, 3525 VOLTAGE_DATA_TWO_BYTE = 1, 3526}; 3527 3528 3529struct atom_voltage_gpio_map_lut 3530{ 3531 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register 3532 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV 3533}; 3534 3535struct atom_gpio_voltage_object_v4 3536{ 3537 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 3538 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode 3539 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table 3540 uint8_t phase_delay_us; // phase delay in unit of micro second 3541 uint8_t reserved; 3542 uint32_t gpio_mask_val; // GPIO Mask value 3543 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1]; 3544}; 3545 3546struct atom_svid2_voltage_object_v4 3547{ 3548 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2 3549 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable 3550 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold 3551 uint8_t psi0_enable; // 3552 uint8_t maxvstep; 3553 uint8_t telemetry_offset; 3554 uint8_t telemetry_gain; 3555 uint16_t reserved1; 3556}; 3557 3558struct atom_merged_voltage_object_v4 3559{ 3560 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER 3561 uint8_t merged_powerrail_type; //enum atom_voltage_type 3562 uint8_t reserved[3]; 3563}; 3564 3565union atom_voltage_object_v4{ 3566 struct atom_gpio_voltage_object_v4 gpio_voltage_obj; 3567 struct atom_i2c_voltage_object_v4 i2c_voltage_obj; 3568 struct atom_svid2_voltage_object_v4 svid2_voltage_obj; 3569 struct atom_merged_voltage_object_v4 merged_voltage_obj; 3570}; 3571 3572struct atom_voltage_objects_info_v4_1 3573{ 3574 struct atom_common_table_header table_header; 3575 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control 3576}; 3577 3578 3579/* 3580 *************************************************************************** 3581 All Command Function structure definition 3582 *************************************************************************** 3583*/ 3584 3585/* 3586 *************************************************************************** 3587 Structures used by asic_init 3588 *************************************************************************** 3589*/ 3590 3591struct asic_init_engine_parameters 3592{ 3593 uint32_t sclkfreqin10khz:24; 3594 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */ 3595}; 3596 3597struct asic_init_mem_parameters 3598{ 3599 uint32_t mclkfreqin10khz:24; 3600 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */ 3601}; 3602 3603struct asic_init_parameters_v2_1 3604{ 3605 struct asic_init_engine_parameters engineparam; 3606 struct asic_init_mem_parameters memparam; 3607}; 3608 3609struct asic_init_ps_allocation_v2_1 3610{ 3611 struct asic_init_parameters_v2_1 param; 3612 uint32_t reserved[16]; 3613}; 3614 3615 3616enum atom_asic_init_engine_flag 3617{ 3618 b3NORMAL_ENGINE_INIT = 0, 3619 b3SRIOV_SKIP_ASIC_INIT = 0x02, 3620 b3SRIOV_LOAD_UCODE = 0x40, 3621}; 3622 3623enum atom_asic_init_mem_flag 3624{ 3625 b3NORMAL_MEM_INIT = 0, 3626 b3DRAM_SELF_REFRESH_EXIT =0x20, 3627}; 3628 3629/* 3630 *************************************************************************** 3631 Structures used by setengineclock 3632 *************************************************************************** 3633*/ 3634 3635struct set_engine_clock_parameters_v2_1 3636{ 3637 uint32_t sclkfreqin10khz:24; 3638 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 3639 uint32_t reserved[10]; 3640}; 3641 3642struct set_engine_clock_ps_allocation_v2_1 3643{ 3644 struct set_engine_clock_parameters_v2_1 clockinfo; 3645 uint32_t reserved[10]; 3646}; 3647 3648 3649enum atom_set_engine_mem_clock_flag 3650{ 3651 b3NORMAL_CHANGE_CLOCK = 0, 3652 b3FIRST_TIME_CHANGE_CLOCK = 0x08, 3653 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result 3654}; 3655 3656/* 3657 *************************************************************************** 3658 Structures used by getengineclock 3659 *************************************************************************** 3660*/ 3661struct get_engine_clock_parameter 3662{ 3663 uint32_t sclk_10khz; // current engine speed in 10KHz unit 3664 uint32_t reserved; 3665}; 3666 3667/* 3668 *************************************************************************** 3669 Structures used by setmemoryclock 3670 *************************************************************************** 3671*/ 3672struct set_memory_clock_parameters_v2_1 3673{ 3674 uint32_t mclkfreqin10khz:24; 3675 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 3676 uint32_t reserved[10]; 3677}; 3678 3679struct set_memory_clock_ps_allocation_v2_1 3680{ 3681 struct set_memory_clock_parameters_v2_1 clockinfo; 3682 uint32_t reserved[10]; 3683}; 3684 3685 3686/* 3687 *************************************************************************** 3688 Structures used by getmemoryclock 3689 *************************************************************************** 3690*/ 3691struct get_memory_clock_parameter 3692{ 3693 uint32_t mclk_10khz; // current engine speed in 10KHz unit 3694 uint32_t reserved; 3695}; 3696 3697 3698 3699/* 3700 *************************************************************************** 3701 Structures used by setvoltage 3702 *************************************************************************** 3703*/ 3704 3705struct set_voltage_parameters_v1_4 3706{ 3707 uint8_t voltagetype; /* enum atom_voltage_type */ 3708 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */ 3709 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */ 3710}; 3711 3712//set_voltage_parameters_v2_1.voltagemode 3713enum atom_set_voltage_command{ 3714 ATOM_SET_VOLTAGE = 0, 3715 ATOM_INIT_VOLTAGE_REGULATOR = 3, 3716 ATOM_SET_VOLTAGE_PHASE = 4, 3717 ATOM_GET_LEAKAGE_ID = 8, 3718}; 3719 3720struct set_voltage_ps_allocation_v1_4 3721{ 3722 struct set_voltage_parameters_v1_4 setvoltageparam; 3723 uint32_t reserved[10]; 3724}; 3725 3726 3727/* 3728 *************************************************************************** 3729 Structures used by computegpuclockparam 3730 *************************************************************************** 3731*/ 3732 3733//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 3734enum atom_gpu_clock_type 3735{ 3736 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00, 3737 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01, 3738 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02, 3739}; 3740 3741struct compute_gpu_clock_input_parameter_v1_8 3742{ 3743 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 3744 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type 3745 uint32_t reserved[5]; 3746}; 3747 3748 3749struct compute_gpu_clock_output_parameter_v1_8 3750{ 3751 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 3752 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly 3753 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac 3754 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac 3755 uint16_t pll_ss_slew_frac; 3756 uint8_t pll_ss_enable; 3757 uint8_t reserved; 3758 uint32_t reserved1[2]; 3759}; 3760 3761 3762 3763/* 3764 *************************************************************************** 3765 Structures used by ReadEfuseValue 3766 *************************************************************************** 3767*/ 3768 3769struct read_efuse_input_parameters_v3_1 3770{ 3771 uint16_t efuse_start_index; 3772 uint8_t reserved; 3773 uint8_t bitslen; 3774}; 3775 3776// ReadEfuseValue input/output parameter 3777union read_efuse_value_parameters_v3_1 3778{ 3779 struct read_efuse_input_parameters_v3_1 efuse_info; 3780 uint32_t efusevalue; 3781}; 3782 3783 3784/* 3785 *************************************************************************** 3786 Structures used by getsmuclockinfo 3787 *************************************************************************** 3788*/ 3789struct atom_get_smu_clock_info_parameters_v3_1 3790{ 3791 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2 3792 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 3793 uint8_t command; // enum of atom_get_smu_clock_info_command 3794 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 3795}; 3796 3797enum atom_get_smu_clock_info_command 3798{ 3799 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0, 3800 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1, 3801 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2, 3802}; 3803 3804enum atom_smu9_syspll0_clock_id 3805{ 3806 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK 3807 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK) 3808 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3809 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 3810 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK 3811 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK 3812 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK 3813 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK 3814 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK 3815 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK 3816 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK 3817}; 3818 3819enum atom_smu11_syspll_id { 3820 SMU11_SYSPLL0_ID = 0, 3821 SMU11_SYSPLL1_0_ID = 1, 3822 SMU11_SYSPLL1_1_ID = 2, 3823 SMU11_SYSPLL1_2_ID = 3, 3824 SMU11_SYSPLL2_ID = 4, 3825 SMU11_SYSPLL3_0_ID = 5, 3826 SMU11_SYSPLL3_1_ID = 6, 3827}; 3828 3829enum atom_smu11_syspll0_clock_id { 3830 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK 3831 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK 3832 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3833 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK 3834 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK 3835 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK 3836}; 3837 3838enum atom_smu11_syspll1_0_clock_id { 3839 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a 3840}; 3841 3842enum atom_smu11_syspll1_1_clock_id { 3843 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b 3844}; 3845 3846enum atom_smu11_syspll1_2_clock_id { 3847 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK 3848}; 3849 3850enum atom_smu11_syspll2_clock_id { 3851 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK 3852}; 3853 3854enum atom_smu11_syspll3_0_clock_id { 3855 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK 3856 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK 3857 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK 3858}; 3859 3860enum atom_smu11_syspll3_1_clock_id { 3861 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK 3862 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK 3863 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK 3864}; 3865 3866enum atom_smu12_syspll_id { 3867 SMU12_SYSPLL0_ID = 0, 3868 SMU12_SYSPLL1_ID = 1, 3869 SMU12_SYSPLL2_ID = 2, 3870 SMU12_SYSPLL3_0_ID = 3, 3871 SMU12_SYSPLL3_1_ID = 4, 3872}; 3873 3874enum atom_smu12_syspll0_clock_id { 3875 SMU12_SYSPLL0_SMNCLK_ID = 0, // SOCCLK 3876 SMU12_SYSPLL0_SOCCLK_ID = 1, // SOCCLK 3877 SMU12_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3878 SMU12_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 3879 SMU12_SYSPLL0_MP2CLK_ID = 4, // MP2CLK 3880 SMU12_SYSPLL0_VCLK_ID = 5, // VCLK 3881 SMU12_SYSPLL0_LCLK_ID = 6, // LCLK 3882 SMU12_SYSPLL0_DCLK_ID = 7, // DCLK 3883 SMU12_SYSPLL0_ACLK_ID = 8, // ACLK 3884 SMU12_SYSPLL0_ISPCLK_ID = 9, // ISPCLK 3885 SMU12_SYSPLL0_SHUBCLK_ID = 10, // SHUBCLK 3886}; 3887 3888enum atom_smu12_syspll1_clock_id { 3889 SMU12_SYSPLL1_DISPCLK_ID = 0, // DISPCLK 3890 SMU12_SYSPLL1_DPPCLK_ID = 1, // DPPCLK 3891 SMU12_SYSPLL1_DPREFCLK_ID = 2, // DPREFCLK 3892 SMU12_SYSPLL1_DCFCLK_ID = 3, // DCFCLK 3893}; 3894 3895enum atom_smu12_syspll2_clock_id { 3896 SMU12_SYSPLL2_Pre_GFXCLK_ID = 0, // Pre_GFXCLK 3897}; 3898 3899enum atom_smu12_syspll3_0_clock_id { 3900 SMU12_SYSPLL3_0_FCLK_ID = 0, // FCLK 3901}; 3902 3903enum atom_smu12_syspll3_1_clock_id { 3904 SMU12_SYSPLL3_1_UMCCLK_ID = 0, // UMCCLK 3905}; 3906 3907struct atom_get_smu_clock_info_output_parameters_v3_1 3908{ 3909 union { 3910 uint32_t smu_clock_freq_hz; 3911 uint32_t syspllvcofreq_10khz; 3912 uint32_t sysspllrefclk_10khz; 3913 }atom_smu_outputclkfreq; 3914}; 3915 3916 3917 3918/* 3919 *************************************************************************** 3920 Structures used by dynamicmemorysettings 3921 *************************************************************************** 3922*/ 3923 3924enum atom_dynamic_memory_setting_command 3925{ 3926 COMPUTE_MEMORY_PLL_PARAM = 1, 3927 COMPUTE_ENGINE_PLL_PARAM = 2, 3928 ADJUST_MC_SETTING_PARAM = 3, 3929}; 3930 3931/* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */ 3932struct dynamic_mclk_settings_parameters_v2_1 3933{ 3934 uint32_t mclk_10khz:24; //Input= target mclk 3935 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 3936 uint32_t reserved; 3937}; 3938 3939/* when command = COMPUTE_ENGINE_PLL_PARAM */ 3940struct dynamic_sclk_settings_parameters_v2_1 3941{ 3942 uint32_t sclk_10khz:24; //Input= target mclk 3943 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 3944 uint32_t mclk_10khz; 3945 uint32_t reserved; 3946}; 3947 3948union dynamic_memory_settings_parameters_v2_1 3949{ 3950 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting; 3951 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting; 3952}; 3953 3954 3955 3956/* 3957 *************************************************************************** 3958 Structures used by memorytraining 3959 *************************************************************************** 3960*/ 3961 3962enum atom_umc6_0_ucode_function_call_enum_id 3963{ 3964 UMC60_UCODE_FUNC_ID_REINIT = 0, 3965 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1, 3966 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2, 3967}; 3968 3969 3970struct memory_training_parameters_v2_1 3971{ 3972 uint8_t ucode_func_id; 3973 uint8_t ucode_reserved[3]; 3974 uint32_t reserved[5]; 3975}; 3976 3977 3978/* 3979 *************************************************************************** 3980 Structures used by setpixelclock 3981 *************************************************************************** 3982*/ 3983 3984struct set_pixel_clock_parameter_v1_7 3985{ 3986 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz. 3987 3988 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 3989 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h, 3990 // indicate which graphic encoder will be used. 3991 uint8_t encoder_mode; // Encoder mode: 3992 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info 3993 uint8_t crtc_id; // enum of atom_crtc_def 3994 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio 3995 uint8_t reserved1[2]; 3996 uint32_t reserved2; 3997}; 3998 3999//ucMiscInfo 4000enum atom_set_pixel_clock_v1_7_misc_info 4001{ 4002 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01, 4003 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02, 4004 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04, 4005 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08, 4006 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30, 4007 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00, 4008 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10, 4009 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20, 4010 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30, 4011 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40, 4012 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80, 4013}; 4014 4015/* deep_color_ratio */ 4016enum atom_set_pixel_clock_v1_7_deepcolor_ratio 4017{ 4018 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 4019 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 4020 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 4021 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 4022}; 4023 4024/* 4025 *************************************************************************** 4026 Structures used by setdceclock 4027 *************************************************************************** 4028*/ 4029 4030// SetDCEClock input parameter for DCE11.2( ELM and BF ) and above 4031struct set_dce_clock_parameters_v2_1 4032{ 4033 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. 4034 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK 4035 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx 4036 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) 4037 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK 4038}; 4039 4040//ucDCEClkType 4041enum atom_set_dce_clock_clock_type 4042{ 4043 DCE_CLOCK_TYPE_DISPCLK = 0, 4044 DCE_CLOCK_TYPE_DPREFCLK = 1, 4045 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock 4046}; 4047 4048//ucDCEClkFlag when ucDCEClkType == DPREFCLK 4049enum atom_set_dce_clock_dprefclk_flag 4050{ 4051 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03, 4052 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00, 4053 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01, 4054 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02, 4055 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03, 4056}; 4057 4058//ucDCEClkFlag when ucDCEClkType == PIXCLK 4059enum atom_set_dce_clock_pixclk_flag 4060{ 4061 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03, 4062 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 4063 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 4064 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 4065 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 4066 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04, 4067}; 4068 4069struct set_dce_clock_ps_allocation_v2_1 4070{ 4071 struct set_dce_clock_parameters_v2_1 param; 4072 uint32_t ulReserved[2]; 4073}; 4074 4075 4076/****************************************************************************/ 4077// Structures used by BlankCRTC 4078/****************************************************************************/ 4079struct blank_crtc_parameters 4080{ 4081 uint8_t crtc_id; // enum atom_crtc_def 4082 uint8_t blanking; // enum atom_blank_crtc_command 4083 uint16_t reserved; 4084 uint32_t reserved1; 4085}; 4086 4087enum atom_blank_crtc_command 4088{ 4089 ATOM_BLANKING = 1, 4090 ATOM_BLANKING_OFF = 0, 4091}; 4092 4093/****************************************************************************/ 4094// Structures used by enablecrtc 4095/****************************************************************************/ 4096struct enable_crtc_parameters 4097{ 4098 uint8_t crtc_id; // enum atom_crtc_def 4099 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 4100 uint8_t padding[2]; 4101}; 4102 4103 4104/****************************************************************************/ 4105// Structure used by EnableDispPowerGating 4106/****************************************************************************/ 4107struct enable_disp_power_gating_parameters_v2_1 4108{ 4109 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ... 4110 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 4111 uint8_t padding[2]; 4112}; 4113 4114struct enable_disp_power_gating_ps_allocation 4115{ 4116 struct enable_disp_power_gating_parameters_v2_1 param; 4117 uint32_t ulReserved[4]; 4118}; 4119 4120/****************************************************************************/ 4121// Structure used in setcrtc_usingdtdtiming 4122/****************************************************************************/ 4123struct set_crtc_using_dtd_timing_parameters 4124{ 4125 uint16_t h_size; 4126 uint16_t h_blanking_time; 4127 uint16_t v_size; 4128 uint16_t v_blanking_time; 4129 uint16_t h_syncoffset; 4130 uint16_t h_syncwidth; 4131 uint16_t v_syncoffset; 4132 uint16_t v_syncwidth; 4133 uint16_t modemiscinfo; 4134 uint8_t h_border; 4135 uint8_t v_border; 4136 uint8_t crtc_id; // enum atom_crtc_def 4137 uint8_t encoder_mode; // atom_encode_mode_def 4138 uint8_t padding[2]; 4139}; 4140 4141 4142/****************************************************************************/ 4143// Structures used by processi2cchanneltransaction 4144/****************************************************************************/ 4145struct process_i2c_channel_transaction_parameters 4146{ 4147 uint8_t i2cspeed_khz; 4148 union { 4149 uint8_t regindex; 4150 uint8_t status; /* enum atom_process_i2c_flag */ 4151 } regind_status; 4152 uint16_t i2c_data_out; 4153 uint8_t flag; /* enum atom_process_i2c_status */ 4154 uint8_t trans_bytes; 4155 uint8_t slave_addr; 4156 uint8_t i2c_id; 4157}; 4158 4159//ucFlag 4160enum atom_process_i2c_flag 4161{ 4162 HW_I2C_WRITE = 1, 4163 HW_I2C_READ = 0, 4164 I2C_2BYTE_ADDR = 0x02, 4165 HW_I2C_SMBUS_BYTE_WR = 0x04, 4166}; 4167 4168//status 4169enum atom_process_i2c_status 4170{ 4171 HW_ASSISTED_I2C_STATUS_FAILURE =2, 4172 HW_ASSISTED_I2C_STATUS_SUCCESS =1, 4173}; 4174 4175 4176/****************************************************************************/ 4177// Structures used by processauxchanneltransaction 4178/****************************************************************************/ 4179 4180struct process_aux_channel_transaction_parameters_v1_2 4181{ 4182 uint16_t aux_request; 4183 uint16_t dataout; 4184 uint8_t channelid; 4185 union { 4186 uint8_t reply_status; 4187 uint8_t aux_delay; 4188 } aux_status_delay; 4189 uint8_t dataout_len; 4190 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 4191}; 4192 4193 4194/****************************************************************************/ 4195// Structures used by selectcrtc_source 4196/****************************************************************************/ 4197 4198struct select_crtc_source_parameters_v2_3 4199{ 4200 uint8_t crtc_id; // enum atom_crtc_def 4201 uint8_t encoder_id; // enum atom_dig_def 4202 uint8_t encode_mode; // enum atom_encode_mode_def 4203 uint8_t dst_bpc; // enum atom_panel_bit_per_color 4204}; 4205 4206 4207/****************************************************************************/ 4208// Structures used by digxencodercontrol 4209/****************************************************************************/ 4210 4211// ucAction: 4212enum atom_dig_encoder_control_action 4213{ 4214 ATOM_ENCODER_CMD_DISABLE_DIG = 0, 4215 ATOM_ENCODER_CMD_ENABLE_DIG = 1, 4216 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08, 4217 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09, 4218 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a, 4219 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13, 4220 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b, 4221 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c, 4222 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d, 4223 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10, 4224 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14, 4225 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F, 4226 ATOM_ENCODER_CMD_LINK_SETUP = 0x11, 4227 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12, 4228}; 4229 4230//define ucPanelMode 4231enum atom_dig_encoder_control_panelmode 4232{ 4233 DP_PANEL_MODE_DISABLE = 0x00, 4234 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01, 4235 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11, 4236}; 4237 4238//ucDigId 4239enum atom_dig_encoder_control_v5_digid 4240{ 4241 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00, 4242 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01, 4243 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02, 4244 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03, 4245 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04, 4246 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05, 4247 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06, 4248 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07, 4249}; 4250 4251struct dig_encoder_stream_setup_parameters_v1_5 4252{ 4253 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4254 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP 4255 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 4256 uint8_t lanenum; // Lane number 4257 uint32_t pclk_10khz; // Pixel Clock in 10Khz 4258 uint8_t bitpercolor; 4259 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc 4260 uint8_t reserved[2]; 4261}; 4262 4263struct dig_encoder_link_setup_parameters_v1_5 4264{ 4265 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4266 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP 4267 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 4268 uint8_t lanenum; // Lane number 4269 uint8_t symclk_10khz; // Symbol Clock in 10Khz 4270 uint8_t hpd_sel; 4271 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 4272 uint8_t reserved[2]; 4273}; 4274 4275struct dp_panel_mode_set_parameters_v1_5 4276{ 4277 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4278 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP 4279 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode 4280 uint8_t reserved1; 4281 uint32_t reserved2[2]; 4282}; 4283 4284struct dig_encoder_generic_cmd_parameters_v1_5 4285{ 4286 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 4287 uint8_t action; // = rest of generic encoder command which does not carry any parameters 4288 uint8_t reserved1[2]; 4289 uint32_t reserved2[2]; 4290}; 4291 4292union dig_encoder_control_parameters_v1_5 4293{ 4294 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param; 4295 struct dig_encoder_stream_setup_parameters_v1_5 stream_param; 4296 struct dig_encoder_link_setup_parameters_v1_5 link_param; 4297 struct dp_panel_mode_set_parameters_v1_5 dppanel_param; 4298}; 4299 4300/* 4301 *************************************************************************** 4302 Structures used by dig1transmittercontrol 4303 *************************************************************************** 4304*/ 4305struct dig_transmitter_control_parameters_v1_6 4306{ 4307 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 4308 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx 4309 union { 4310 uint8_t digmode; // enum atom_encode_mode_def 4311 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" 4312 } mode_laneset; 4313 uint8_t lanenum; // Lane number 1, 2, 4, 8 4314 uint32_t symclk_10khz; // Symbol Clock in 10Khz 4315 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned 4316 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 4317 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h 4318 uint8_t reserved; 4319 uint32_t reserved1; 4320}; 4321 4322struct dig_transmitter_control_ps_allocation_v1_6 4323{ 4324 struct dig_transmitter_control_parameters_v1_6 param; 4325 uint32_t reserved[4]; 4326}; 4327 4328//ucAction 4329enum atom_dig_transmitter_control_action 4330{ 4331 ATOM_TRANSMITTER_ACTION_DISABLE = 0, 4332 ATOM_TRANSMITTER_ACTION_ENABLE = 1, 4333 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2, 4334 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3, 4335 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4, 4336 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5, 4337 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6, 4338 ATOM_TRANSMITTER_ACTION_INIT = 7, 4339 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8, 4340 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9, 4341 ATOM_TRANSMITTER_ACTION_SETUP = 10, 4342 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11, 4343 ATOM_TRANSMITTER_ACTION_POWER_ON = 12, 4344 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13, 4345}; 4346 4347// digfe_sel 4348enum atom_dig_transmitter_control_digfe_sel 4349{ 4350 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01, 4351 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02, 4352 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04, 4353 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08, 4354 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10, 4355 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20, 4356 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40, 4357}; 4358 4359 4360//ucHPDSel 4361enum atom_dig_transmitter_control_hpd_sel 4362{ 4363 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00, 4364 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01, 4365 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02, 4366 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03, 4367 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04, 4368 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05, 4369 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06, 4370}; 4371 4372// ucDPLaneSet 4373enum atom_dig_transmitter_control_dplaneset 4374{ 4375 DP_LANE_SET__0DB_0_4V = 0x00, 4376 DP_LANE_SET__0DB_0_6V = 0x01, 4377 DP_LANE_SET__0DB_0_8V = 0x02, 4378 DP_LANE_SET__0DB_1_2V = 0x03, 4379 DP_LANE_SET__3_5DB_0_4V = 0x08, 4380 DP_LANE_SET__3_5DB_0_6V = 0x09, 4381 DP_LANE_SET__3_5DB_0_8V = 0x0a, 4382 DP_LANE_SET__6DB_0_4V = 0x10, 4383 DP_LANE_SET__6DB_0_6V = 0x11, 4384 DP_LANE_SET__9_5DB_0_4V = 0x18, 4385}; 4386 4387 4388 4389/****************************************************************************/ 4390// Structures used by ExternalEncoderControl V2.4 4391/****************************************************************************/ 4392 4393struct external_encoder_control_parameters_v2_4 4394{ 4395 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 4396 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 4397 uint8_t action; // 4398 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 4399 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 4400 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 4401 uint8_t hpd_id; 4402}; 4403 4404 4405// ucAction 4406enum external_encoder_control_action_def 4407{ 4408 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00, 4409 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01, 4410 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07, 4411 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f, 4412 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10, 4413 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11, 4414 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12, 4415 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14, 4416}; 4417 4418// ucConfig 4419enum external_encoder_control_v2_4_config_def 4420{ 4421 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03, 4422 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00, 4423 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01, 4424 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02, 4425 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03, 4426 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70, 4427 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00, 4428 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10, 4429 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20, 4430}; 4431 4432struct external_encoder_control_ps_allocation_v2_4 4433{ 4434 struct external_encoder_control_parameters_v2_4 sExtEncoder; 4435 uint32_t reserved[2]; 4436}; 4437 4438 4439/* 4440 *************************************************************************** 4441 AMD ACPI Table 4442 4443 *************************************************************************** 4444*/ 4445 4446struct amd_acpi_description_header{ 4447 uint32_t signature; 4448 uint32_t tableLength; //Length 4449 uint8_t revision; 4450 uint8_t checksum; 4451 uint8_t oemId[6]; 4452 uint8_t oemTableId[8]; //UINT64 OemTableId; 4453 uint32_t oemRevision; 4454 uint32_t creatorId; 4455 uint32_t creatorRevision; 4456}; 4457 4458struct uefi_acpi_vfct{ 4459 struct amd_acpi_description_header sheader; 4460 uint8_t tableUUID[16]; //0x24 4461 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 4462 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 4463 uint32_t reserved[4]; //0x3C 4464}; 4465 4466struct vfct_image_header{ 4467 uint32_t pcibus; //0x4C 4468 uint32_t pcidevice; //0x50 4469 uint32_t pcifunction; //0x54 4470 uint16_t vendorid; //0x58 4471 uint16_t deviceid; //0x5A 4472 uint16_t ssvid; //0x5C 4473 uint16_t ssid; //0x5E 4474 uint32_t revision; //0x60 4475 uint32_t imagelength; //0x64 4476}; 4477 4478 4479struct gop_vbios_content { 4480 struct vfct_image_header vbiosheader; 4481 uint8_t vbioscontent[1]; 4482}; 4483 4484struct gop_lib1_content { 4485 struct vfct_image_header lib1header; 4486 uint8_t lib1content[1]; 4487}; 4488 4489 4490 4491/* 4492 *************************************************************************** 4493 Scratch Register definitions 4494 Each number below indicates which scratch regiser request, Active and 4495 Connect all share the same definitions as display_device_tag defines 4496 *************************************************************************** 4497*/ 4498 4499enum scratch_register_def{ 4500 ATOM_DEVICE_CONNECT_INFO_DEF = 0, 4501 ATOM_BL_BRI_LEVEL_INFO_DEF = 2, 4502 ATOM_ACTIVE_INFO_DEF = 3, 4503 ATOM_LCD_INFO_DEF = 4, 4504 ATOM_DEVICE_REQ_INFO_DEF = 5, 4505 ATOM_ACC_CHANGE_INFO_DEF = 6, 4506 ATOM_PRE_OS_MODE_INFO_DEF = 7, 4507 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers. 4508 ATOM_INTERNAL_TIMER_INFO_DEF = 10, 4509}; 4510 4511enum scratch_device_connect_info_bit_def{ 4512 ATOM_DISPLAY_LCD1_CONNECT =0x0002, 4513 ATOM_DISPLAY_DFP1_CONNECT =0x0008, 4514 ATOM_DISPLAY_DFP2_CONNECT =0x0080, 4515 ATOM_DISPLAY_DFP3_CONNECT =0x0200, 4516 ATOM_DISPLAY_DFP4_CONNECT =0x0400, 4517 ATOM_DISPLAY_DFP5_CONNECT =0x0800, 4518 ATOM_DISPLAY_DFP6_CONNECT =0x0040, 4519 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8, 4520 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff, 4521}; 4522 4523enum scratch_bl_bri_level_info_bit_def{ 4524 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8, 4525#ifndef _H2INC 4526 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00, 4527 ATOM_DEVICE_DPMS_STATE =0x00010000, 4528#endif 4529}; 4530 4531enum scratch_active_info_bits_def{ 4532 ATOM_DISPLAY_LCD1_ACTIVE =0x0002, 4533 ATOM_DISPLAY_DFP1_ACTIVE =0x0008, 4534 ATOM_DISPLAY_DFP2_ACTIVE =0x0080, 4535 ATOM_DISPLAY_DFP3_ACTIVE =0x0200, 4536 ATOM_DISPLAY_DFP4_ACTIVE =0x0400, 4537 ATOM_DISPLAY_DFP5_ACTIVE =0x0800, 4538 ATOM_DISPLAY_DFP6_ACTIVE =0x0040, 4539 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff, 4540}; 4541 4542enum scratch_device_req_info_bits_def{ 4543 ATOM_DISPLAY_LCD1_REQ =0x0002, 4544 ATOM_DISPLAY_DFP1_REQ =0x0008, 4545 ATOM_DISPLAY_DFP2_REQ =0x0080, 4546 ATOM_DISPLAY_DFP3_REQ =0x0200, 4547 ATOM_DISPLAY_DFP4_REQ =0x0400, 4548 ATOM_DISPLAY_DFP5_REQ =0x0800, 4549 ATOM_DISPLAY_DFP6_REQ =0x0040, 4550 ATOM_REQ_INFO_DEVICE_MASK =0x0fff, 4551}; 4552 4553enum scratch_acc_change_info_bitshift_def{ 4554 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4, 4555 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6, 4556}; 4557 4558enum scratch_acc_change_info_bits_def{ 4559 ATOM_ACC_CHANGE_ACC_MODE =0x00000010, 4560 ATOM_ACC_CHANGE_LID_STATUS =0x00000040, 4561}; 4562 4563enum scratch_pre_os_mode_info_bits_def{ 4564 ATOM_PRE_OS_MODE_MASK =0x00000003, 4565 ATOM_PRE_OS_MODE_VGA =0x00000000, 4566 ATOM_PRE_OS_MODE_VESA =0x00000001, 4567 ATOM_PRE_OS_MODE_GOP =0x00000002, 4568 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C, 4569 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0, 4570 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100, 4571 ATOM_ASIC_INIT_COMPLETE =0x00000200, 4572#ifndef _H2INC 4573 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000, 4574#endif 4575}; 4576 4577 4578 4579/* 4580 *************************************************************************** 4581 ATOM firmware ID header file 4582 !! Please keep it at end of the atomfirmware.h !! 4583 *************************************************************************** 4584*/ 4585#include "atomfirmwareid.h" 4586#pragma pack() 4587 4588#endif 4589 4590